公开(公告)号：US20100102395A1

公开(公告)日：2010-04-29

申请号：US12572646

申请日：2009-10-02

申请人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

发明人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823857

摘要： Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of a work-function controlling material into the interface of the first insulating film.

摘要翻译： 提供了能够分别具有适合于nMOS和pMOS的具有良好形状并具有平坦带电压的单个金属/双高k结构的半导体器件。 根据本发明的一个实施例的半导体器件具有第一导电型MOSFET和第二导电型MOSFET。 第一导电型MOSFET和第二导电型MOSFET分别配置有形成在半导体基板上的第一绝缘膜，形成在第一绝缘膜上并且由具有比第一绝缘膜高的介电常数的绝缘材料制成的第二绝缘膜， 栅电极形成在第二绝缘膜上，并且具有作为栅电极的下层的含有扩散到第二绝缘膜中以控制其功函的材料的金属层。 第二导电型MOSFET还具有形成在第一绝缘膜和第二绝缘膜之间的扩散阻挡膜，以防止功函数控制材料扩散到第一绝缘膜的界面中。

公开(公告)号：US08796780B2

公开(公告)日：2014-08-05

申请号：US12572646

申请日：2009-10-02

申请人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

发明人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

IPC分类号： H01L29/72

CPC分类号： H01L21/823828 ,  H01L21/823857

摘要： Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of a work-function controlling material into the interface of the first insulating film.

摘要翻译： 提供了能够分别具有适合于nMOS和pMOS的具有良好形状并具有平坦带电压的单个金属/双高k结构的半导体器件。 根据本发明的一个实施例的半导体器件具有第一导电型MOSFET和第二导电型MOSFET。 第一导电型MOSFET和第二导电型MOSFET分别配置有形成在半导体基板上的第一绝缘膜，形成在第一绝缘膜上并且由具有比第一绝缘膜高的介电常数的绝缘材料制成的第二绝缘膜，以及 栅电极形成在第二绝缘膜上，并且具有作为栅电极的下层的含有扩散到第二绝缘膜中以控制其功函的材料的金属层。 第二导电型MOSFET还具有形成在第一绝缘膜和第二绝缘膜之间的扩散阻挡膜，以防止功函数控制材料扩散到第一绝缘膜的界面中。

公开(公告)号：US20080308869A1

公开(公告)日：2008-12-18

申请号：US12194631

申请日：2008-08-20

申请人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US20070007602A1

公开(公告)日：2007-01-11

申请号：US11478669

申请日：2006-07-03

申请人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/94

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US08552507B2

公开(公告)日：2013-10-08

申请号：US13515500

申请日：2009-12-24

申请人： Jiro Yugami

发明人： Jiro Yugami

IPC分类号： H01L21/70

CPC分类号： H01L21/823857 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z1 and a first high-dielectric film hk1, and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z1 and a second high-dielectric film hk2. The first high-dielectric film hk1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.

摘要翻译： 布置在硅衬底1的pMIS区域Rp中的p型MIS晶体管Qp包括pMIS栅极电极GEp，其形成为将由第一绝缘膜z1和第一高介电膜hk1形成的pMIS栅极绝缘膜GIp ，并且配置在nMIS区域Rn中的n型MIS晶体管Qn包括形成为以由第一绝缘膜z1和第二高介电膜hk2形成的nMIS栅极绝缘膜GIn形成的nMIS栅电极GEn。 第一高电介质膜hk1由主要由铪和含有铝，钛或钽的氧构成的绝缘膜形成。 此外，第二高电介质膜hk2由主要由铪，硅和氧制成的绝缘膜形成，其含有Ia，IIa和IIIa族中任一种的元素。

公开(公告)号：US07863125B2

公开(公告)日：2011-01-04

申请号：US12492648

申请日：2009-06-26

申请人： Shimpei Tsujikawa ,  Yasuhiko Akamatsu ,  Hiroshi Umeda ,  Jiro Yugami ,  Masaharu Mizutani ,  Masao Inoue ,  Junichi Tsuchimoto ,  Kouji Nomura

发明人： Shimpei Tsujikawa ,  Yasuhiko Akamatsu ,  Hiroshi Umeda ,  Jiro Yugami ,  Masaharu Mizutani ,  Masao Inoue ,  Junichi Tsuchimoto ,  Kouji Nomura

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857

摘要： The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

摘要翻译： 在这种CMOS型半导体器件的制造方法中，能够抑制在栅极电极中含有硼的情况下，从pMOS晶体管的栅电极到半导体衬底的硼渗透，同时能够提高pMOS的NBTI寿命 提供了晶体管，而不降低nMOS晶体管的性能。 关于本发明的CMOS型半导体器件的制造方法具有以下工序。 卤素引入pMOS晶体管形成区域的半导体衬底。 接下来，在pMOS晶体管形成区域的半导体衬底上形成栅极绝缘膜。 接下来，将氮引入到栅极绝缘膜。

公开(公告)号：US06982468B2

公开(公告)日：2006-01-03

申请号：US10942014

申请日：2004-09-16

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

公开(公告)号：US06521943B1

公开(公告)日：2003-02-18

申请号：US09520346

申请日：2000-03-07

申请人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

发明人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

摘要翻译： 公开了一种半导体器件（例如非易失性半导体存储器件）及其形成方法。 该器件包括在栅极绝缘膜上具有非晶硅膜的第一层或多晶硅薄膜或非晶硅和多晶硅的组合的膜的栅电极（例如，浮栅电极）。 当膜包括多晶硅时，膜的厚度小于10nm。 可以在第一层上或覆盖第一层上提供较厚的多晶硅膜。 存储器件可以显着增加写入/擦除电流，而不会在施加应力之后增加低电场漏电流，这反过来大大降低了写入/擦除时间。 在形成半导体器件时，可以在栅极绝缘膜上提供薄的非晶或多晶硅膜，以及设置在非晶硅膜上的薄绝缘膜，其上设置有较厚的多晶硅膜或覆盖薄绝缘膜。 在薄硅膜是非晶硅的情况下，其然后可以多晶化，尽管不需要。 还公开了基于层厚度的非晶硅层的选择性结晶的技术。

公开(公告)号：US6144062A

公开(公告)日：2000-11-07

申请号：US41793

申请日：1998-03-13

申请人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

发明人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

公开(公告)号：US5091761A

公开(公告)日：1992-02-25

申请号：US384821

申请日：1989-07-25

申请人： Atsushi Hiraiwa ,  Shinichiro Kimura ,  Toshiyuki Mine ,  Takashi Kobayashi ,  Tokuo Kure ,  Shinpei Iijima ,  Jiro Yugami

发明人： Atsushi Hiraiwa ,  Shinichiro Kimura ,  Toshiyuki Mine ,  Takashi Kobayashi ,  Tokuo Kure ,  Shinpei Iijima ,  Jiro Yugami

IPC分类号： H01L27/108

CPC分类号： H01L27/10808

摘要： Disclosed is a semiconductor device including a charge storage capacitor having a storage electrode which is electrically connected to a switching transistor through a contact hole provided in an insulator and which has a greater film thickness than the radius of the contact hole, at least a part of the storage electrode being disposed above a data line. It is possible to reduce the memory cell area while preventing lowering in the capacitance, and thus realize high density and high integration of semiconductor devices.

摘要翻译： 公开了一种半导体器件，包括具有存储电极的电荷存储电容器，该存储电极通过设置在绝缘体中的接触孔与开关晶体管电连接并且具有比接触孔的半径更大的膜厚度，至少部分 所述存储电极设置在数据线的上方。 可以在防止电容降低的同时减小存储单元面积，从而实现半导体器件的高密度和高集成度。