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21 条记录 (耗时 0.022 秒)

    Semiconductor integrated circuit, logic operation circuit, and flip flop
    1.
    发明授权
    Semiconductor integrated circuit, logic operation circuit, and flip flop 失效
    半导体集成电路，逻辑运算电路和触发器

    公开(公告)号：US06750680B2

    公开(公告)日：2004-06-15

    申请号：US09883959

    申请日：2001-06-20

    申请人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

    发明人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

    IPC分类号： H03K19096

    CPC分类号： H03K19/01707 ,  H03K19/0016

    摘要： There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

    摘要翻译： 提供了能够高速运行并且具有泄漏电流降低的半导体集成电路，逻辑运算电路和触发器。在根据本发明的半导体集成电路中，仅在关键路径上的门电路 由具有低阈值电压的晶体管与具有高阈值电压的晶体管组合而获得的MT门单元构成，并且任何其它门电路由具有高阈值电压的晶体管构成。 因此，关键路径上的门电路可以高速运转，能够抑制整体的漏电流，从而降低功耗。

    Semiconductor device including current mirror circuit
    9.
    发明授权
    Semiconductor device including current mirror circuit 有权
    半导体器件包括电流镜电路

    公开(公告)号：US07248100B2

    公开(公告)日：2007-07-24

    申请号：US11171316

    申请日：2005-07-01

    申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

    发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

    IPC分类号： G05F1/10

    CPC分类号： G05F3/262

    摘要： A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.

    摘要翻译： 公开了一种包括多个电流镜电路的半导体器件。 电流镜电路分别具有参考输入端和输出端。 每个参考输入端子具有不同电流值的电流。 电流镜电路的每个输出端连接到电流输出端。 电流镜电路的输出电流由控制电路控制。

    Semiconductor memory with current distributor
    10.
    发明授权
    Semiconductor memory with current distributor 失效
    半导体存储器与电流分配器

    公开(公告)号：US06466503B2

    公开(公告)日：2002-10-15

    申请号：US09949652

    申请日：2001-09-12

    申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

    发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

    IPC分类号： G11C706

    CPC分类号： G11C17/12

    摘要： A semiconductor memory has paired first and second bit lines one of which passes a current representing data stored in a selected memory cell. If the first bit line transfers the current representing the data stored in the memory cell, the second bit line transfers a current representing data stored in a dummy cell. If the second bit line transfers the current representing the data stored in the memory cell, the first bit line transfers the current representing the data stored in the dummy cell. The current transferred through the first bit line is divided into partial currents, and the current transferred through the second bit line is also divided into partial currents. It is determined whether or not the current representing the data stored in the memory cell is passed through the first bit line. If it is determined that the first bit line passes the current representing the data stored in the memory cell, the partial currents from the first bit line are recombined to provide an output and one of the partial currents from the second bit line is selected to provide another output. If it is determined that the first bit line does not pass the current representing the data stored in the memory cell, i.e., the first bit line passes the current representing the data stored in the dummy cell, the partial currents from the second bit line are recombined to provide an output and one of the partial currents from the first bit line is selected to provide another output.

    摘要翻译： 半导体存储器配对第一和第二位线，其中一个通过表示存储在所选存储单元中的数据的电流。 如果第一位线传送表示存储在存储单元中的数据的电流，则第二位线传送表示存储在虚拟单元中的数据的电流。 如果第二位线传送表示存储在存储单元中的数据的电流，则第一位线传送表示存储在虚拟单元中的数据的电流。 通过第一位线传输的电流被分成部分电流，并且通过第二位线传输的电流也被分为部分电流。 确定表示存储在存储单元中的数据的电流是否通过第一位线。 如果确定第一位线通过表示存储在存储单元中的数据的电流，则来自第一位线的部分电流被重组以提供输出，并且选择来自第二位线的部分电流中的一个以提供 另一个输出。 如果确定第一位线未通过表示存储在存储单元中的数据的电流，即，第一位线通过表示存储在虚拟单元中的数据的电流，则来自第二位线的部分电流为 重新组合以提供输出，并且选择来自第一位线的部分电流中的一个以提供另一输出。