公开(公告)号：US20050035802A1

公开(公告)日：2005-02-17

申请号：US10946398

申请日：2004-09-21

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H03K3/02

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

公开(公告)号：US07088161B2

公开(公告)日：2006-08-08

申请号：US10948349

申请日：2004-09-23

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H03K3/356

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

公开(公告)号：US07109771B2

公开(公告)日：2006-09-19

申请号：US10946398

申请日：2004-09-21

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H03K3/356

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

公开(公告)号：US20050035803A1

公开(公告)日：2005-02-17

申请号：US10948349

申请日：2004-09-23

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H03K3/02

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

公开(公告)号：US06586982B2

公开(公告)日：2003-07-01

申请号：US09961027

申请日：2001-09-21

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H03K3037

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

摘要翻译： 组合电路在响应于控制信号向其供电的有效状态和其中断电的无效状态之间切换。 连接到组合电路的输入端的触发器电路响应于时钟信号存储组合电路的输出信号。 组合电路通过紧接在触发器电路根据时钟信号工作之前的控制信号设置为工作状态。

公开(公告)号：US06861882B2

公开(公告)日：2005-03-01

申请号：US10342045

申请日：2003-01-14

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H03L7/00

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

摘要翻译： 组合电路在响应于控制信号向其供电的有效状态和其中断电的无效状态之间切换。 连接到组合电路的输入端的触发器电路响应于时钟信号存储组合电路的输出信号。 组合电路通过紧接在触发器电路根据时钟信号工作之前的控制信号设置为工作状态。

公开(公告)号：US06750680B2

公开(公告)日：2004-06-15

申请号：US09883959

申请日：2001-06-20

申请人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

发明人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

IPC分类号： H03K19096

CPC分类号： H03K19/01707 ,  H03K19/0016

摘要： There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

摘要翻译： 提供了能够高速运行并且具有泄漏电流降低的半导体集成电路，逻辑运算电路和触发器。在根据本发明的半导体集成电路中，仅在关键路径上的门电路 由具有低阈值电压的晶体管与具有高阈值电压的晶体管组合而获得的MT门单元构成，并且任何其它门电路由具有高阈值电压的晶体管构成。 因此，关键路径上的门电路可以高速运转，能够抑制整体的漏电流，从而降低功耗。

公开(公告)号：US06493856B2

公开(公告)日：2002-12-10

申请号：US09895376

申请日：2001-06-29

申请人： Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Masayuki Koizumi ,  Hidemasa Zama ,  Toshiyuki Furusawa

发明人： Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Masayuki Koizumi ,  Hidemasa Zama ,  Toshiyuki Furusawa

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

摘要翻译： 自动电路生成方法和装置（1）通过在备用状态和活动状态期间减少泄漏电流来提供期望的电路性能，其中仅具有高Vth晶体管和低Vth晶体管的高电压和Mt单元的电池 翻译者在逻辑电路中最佳混合。 因此，可以在根据LSI布局设计的小型化产生的设计阶段中有效地抑制泄漏电流，并且还降低对LSI的电源电压。

公开(公告)号：US20110006557A1

公开(公告)日：2011-01-13

申请号：US12920213

申请日：2009-05-08

申请人： Masayuki Koizumi ,  Yusaku Furukawa

发明人： Masayuki Koizumi ,  Yusaku Furukawa

IPC分类号： B60R7/04

CPC分类号： B60R7/04 ,  B60K2350/925 ,  B60K2350/943 ,  B60R13/0256 ,  B60R13/0262 ,  B60R2013/0293

摘要： A mounting structure for vehicle interior parts includes a console member and a shift panel having an upper panel and a lower panel. An insertion portion that is inserted into a dent formed in a rear end of the console member is provided on a rear end of the lower panel. Left and right outer side surfaces of the insertion portion of the lower panel and left and right inner side surfaces of the dent of the console member are configured to be engageable by inserting engaging projections into engaging recesses. The engaging recesses are provided so as to restrict movements of the engaging projections in their longitudinal direction, and to allow positional deviation of the engaging projections in the vertical direction.

摘要翻译： 用于车辆内部部件的安装结构包括控制台部件和具有上板和下板的换挡板。 插入到形成在控制台构件的后端的凹部中的插入部设置在下板的后端。 下侧板的插入部的左外侧面和右外侧面以及控制台部件的凹部的左右内侧面构成为能够通过将卡定突起插入到卡合凹部中而卡合。 接合凹部被设置成限制接合突起在其纵向方向上的移动，并且允许接合突起在垂直方向上的位置偏移。

公开(公告)号：US07468625B2

公开(公告)日：2008-12-23

申请号：US11773996

申请日：2007-07-06

申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.

摘要翻译： 公开了一种包括多个电流镜电路的半导体器件。 电流镜电路分别具有参考输入端和输出端。 每个参考输入端子具有不同电流值的电流。 电流镜电路的每个输出端连接到电流输出端。 电流镜电路的输出电流由控制电路控制。