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公开(公告)号：US08508986B2
公开(公告)日：2013-08-13
申请号：US13188924
申请日：2011-07-22
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.
摘要翻译： 一种具有第一和第二数字线驱动器和位线驱动器的半导体器件。 当从外部输入一个段的地址时，段解码器选择与地址相对应的一个段，并将其与所选择的第一位数字线驱动器相连。 当从外部输入两个或更多个段的地址时，段解码器选择对应于地址的两个或多个段，并将所选择的两个或多个段耦合到相应的数字线路驱动器。
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公开(公告)号：US20120075921A1
公开(公告)日：2012-03-29
申请号：US13188924
申请日：2011-07-22
IPC分类号： G11C11/02
CPC分类号： G11C8/12 , G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively.
摘要翻译： 提供一种使用能够实现正常写入操作的段写入方法的半导体器件。 第一DL驱动器和第二DL驱动器各自引起磁化电流流过所选块的数字线。 BL驱动器使写入电流在与所选择的段中的所有位线对应的数据信号逻辑的方向上流动，并将数据信号写入所选择的块的存储单元。 段解码器当从外部输入一个段的地址时，选择与该地址相对应的一个段，并将其与所选择的第一DL驱动器相连，并且当两个或多个段的地址已被 从外部输入，选择对应于地址的两个或更多个段，并将所选择的两个或多个段分别耦合到第一DL驱动器和第二DL驱动器。
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公开(公告)号：US08139402B2
公开(公告)日：2012-03-20
申请号：US12349542
申请日：2009-01-07
IPC分类号： G11C11/14
CPC分类号： H01L27/228 , H01L43/08
摘要： A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.
摘要翻译： 提供了一种磁存储器件，其中即使具有不对称形状和局部通孔的记录层形成在具有允许的足够距离的带布线之间，也可以抑制磁存储器件的尺寸的增加。 磁存储器件包括带状布线，本地通孔和磁记录元件（TMR元件）。 TMR元件包括固定层和记录层。 记录层的平面形状相对于记录层的易磁化轴的方向是不对称的，并且相对于垂直于易磁化轴的对称轴对称。 在记录层的更靠近记录层的中心的一侧的记录层的轮廓部分与局部通孔形成侧相对。
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公开(公告)号：US20090174016A1
公开(公告)日：2009-07-09
申请号：US12349542
申请日：2009-01-07
IPC分类号： H01L29/82
CPC分类号： H01L27/228 , H01L43/08
摘要： A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.
摘要翻译： 提供了一种磁存储器件，其中即使具有不对称形状和局部通孔的记录层形成在具有允许的足够距离的带布线之间，也可以抑制磁存储器件的尺寸的增加。 磁存储器件包括带状布线，本地通孔和磁记录元件（TMR元件）。 TMR元件包括固定层和记录层。 记录层的平面形状相对于记录层的易磁化轴的方向是不对称的，并且相对于垂直于易磁化轴的对称轴对称。 在记录层的更靠近记录层的中心的一侧的记录层的轮廓部分与局部通孔形成侧相对。
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公开(公告)号：US20070159870A1
公开(公告)日：2007-07-12
申请号：US11645610
申请日：2006-12-27
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/31 , G11C2213/79
摘要： Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.
摘要翻译： 自旋注入磁存储单元的源极线与字线平行地布置，用于一次执行数据多位读写。 在写入操作中，源极线电位以预定的顺序改变，使得共同连接到多个选择的存储器单元的源极线被设置为仅在操作序列的每个阶段中在一个方向上传递电流。 对于数据写入序列，根据写入数据顺序地使电流流过存储器单元，或者存储单元在写入之前具有设置为初始电阻状态的电阻状态，然后根据写入数据快速变为状态 可以在磁存储器中实现写入，而不增加存储单元布局区域。
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公开(公告)号：US07436699B2
公开(公告)日：2008-10-14
申请号：US11645610
申请日：2006-12-27
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/31 , G11C2213/79
摘要： Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.
摘要翻译： 自旋注入磁存储单元的源极线与字线平行地布置，用于一次执行数据多位读写。 在写入操作中，源极线电位以预定的顺序改变，使得共同连接到多个选择的存储器单元的源极线被设置为仅在操作序列的每个阶段中在一个方向上传递电流。 对于数据写入序列，根据写入数据顺序地使电流流过存储器单元，或者存储单元在写入之前具有设置为初始电阻状态的电阻状态，然后根据写入数据快速变为状态 可以在磁存储器中实现写入，而不增加存储单元布局区域。
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公开(公告)号：US07872907B2
公开(公告)日：2011-01-18
申请号：US12340513
申请日：2008-12-19
申请人： Shota Okayama , Yasumitsu Murai
发明人： Shota Okayama , Yasumitsu Murai
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C5/025 , G11C11/1653 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C13/0023 , G11C13/0028
摘要： There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.
摘要翻译： 提供了能够进行高速数据读取并减小用于激活字线的驱动电路的面积的半导体器件。 通过通过具有低电阻并且在多个点处耦合到字线的公共字线的信号传输，可以高速读取数据。 此外，由于公共字线被提供为多个存储块的公共信号，所以字线驱动器可以被提供给存储器块公用。 此外，通过配置与子数字对应的锁存电路来保持公共字线的有效状态，可以通过公共字线在数据写入期间发送行选择信号，从而减少金属布线 层。
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公开(公告)号：US20090168502A1
公开(公告)日：2009-07-02
申请号：US12340513
申请日：2008-12-19
申请人： Shota Okayama , Yasumitsu Murai
发明人： Shota Okayama , Yasumitsu Murai
CPC分类号： H01L27/228 , G11C5/025 , G11C11/1653 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C13/0023 , G11C13/0028
摘要： There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.
摘要翻译： 提供了能够进行高速数据读取并减小用于激活字线的驱动电路的面积的半导体器件。 通过通过具有低电阻并且在多个点处耦合到字线的公共字线的信号传输，可以高速读取数据。 此外，由于公共字线被提供为多个存储块的公共信号，所以字线驱动器可以被提供给存储器块公用。 此外，通过配置与子数字对应的锁存电路来保持公共字线的有效状态，可以通过公共字线在数据写入期间发送行选择信号，从而减少金属布线 层。
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公开(公告)号：US5815462A
公开(公告)日：1998-09-29
申请号：US800905
申请日：1997-02-12
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/409 , G11C8/00
CPC分类号： G11C7/225 , G11C7/1039 , G11C7/1072 , G11C7/22
摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.
摘要翻译： 用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。 可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。 内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过 输出缓冲区。 提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。
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公开(公告)号：US06496429B2
公开(公告)日：2002-12-17
申请号：US09988173
申请日：2001-11-19
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C29/1201 , G11C29/48
摘要： A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.
摘要翻译： 将备用存储单元数据输入/输出到半导体存储器件的外部的备用数据端子和用于输入/输出正常存储单元数据的端子彼此分开设置。 在测试模式中，数据终端并联连接到内部数据线对，并且备用数据线对耦合到备用数据终端。 因此，可以缩短用于检测半导体存储器件中的有缺陷的位的测试时间。
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