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    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130234156A1

    公开(公告)日：2013-09-12

    申请号：US13885131

    申请日：2011-10-17

    申请人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

    发明人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/66734 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/78

    摘要： It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n−-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n−-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.

    摘要翻译： 本发明的目的是提高具有开口的垂直半导体器件的击穿电压特性，并且在开口中包括由二维电子气形成的沟道。 GaN基叠层15包括n型GaN漂移层4 / p型GaN势垒层6 / n +型GaN接触层7.开口28从顶层延伸并到达n型GaN漂移 该半导体器件包括重新生长层27，其被覆盖以覆盖开口的壁表面和底部，再生长层27包括电子漂移层22和电子源层26，源电极S位于 开口，位于开口中的再生长层上的栅极电极G和位于开口底部的底部绝缘层37。

    Semiconductor device and method for manufacturing same
    4.
    发明授权
    Semiconductor device and method for manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US08227810B2

    公开(公告)日：2012-07-24

    申请号：US13126569

    申请日：2010-07-09

    申请人： Masaya Okada ,  Makoto Kiyama ,  Seiji Yaegashi ,  Ken Nakata

    发明人： Masaya Okada ,  Makoto Kiyama ,  Seiji Yaegashi ,  Ken Nakata

    IPC分类号： H01L29/15

    CPC分类号： H01L29/8725 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8128 ,  H01L29/872

    摘要： There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device.In the present invention, the semiconductor device includes an n+-type GaN substrate 1 having a GaN layer that is in ohmic contact with a supporting substrate, a FET having an n−-type GaN drift layer 2 in a first region R1, and an SBD having an anode electrode in a second region R2, the anode electrode being in Schottky contact with the n−-type GaN drift layer 2. The FET and the SBD are arranged in parallel. A drain electrode D of the FET and a cathode electrode C of the SBD are formed on the back of the n+-type GaN substrate 1.

    摘要翻译： 提供了一种具有抗浪涌电压等的旁路保护单元的半导体器件，具有良好的耐压特性和低导通电阻（低导通电压），结构简单，用于大电流目的 以及半导体装置的制造方法。 在本发明中，半导体器件包括具有与支撑衬底欧姆接触的GaN层的n +型GaN衬底1，在第一区域R1中具有n型GaN漂移层2的FET和 SBD在第二区域R2中具有阳极电极，阳极与n型GaN漂移层2肖特基接触.FET和SBD平行布置。 FET的漏电极D和SBD的阴极电极C形成在n +型GaN衬底1的背面。

    Vertical GaN-based semiconductor device
    5.
    发明授权
    Vertical GaN-based semiconductor device 有权
    垂直GaN基半导体器件

    公开(公告)号：US08969920B2

    公开(公告)日：2015-03-03

    申请号：US13824248

    申请日：2011-07-06

    申请人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

    发明人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

    IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423

    CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

    摘要： A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.

    摘要翻译： 提供了通过确定地固定p型GaN势垒层的电位可以稳定地提高夹断特性和击穿电压特性的垂直半导体器件。 半导体器件包括具有开口的GaN基层叠层，包含覆盖开口壁面的沟道的再生长层，与源电极欧姆接触的n +型源极，p 位于p型GaN势垒层和n +型源极层之间的p +型GaN基辅助层。 p +型GaN基辅助层和n +型源极层形成隧道结，以将p型GaN阻挡层的电位固定在源极电位。

    Semiconductor device and method for producing same
    7.
    发明授权
    Semiconductor device and method for producing same 有权
    半导体装置及其制造方法

    公开(公告)号：US08896058B2

    公开(公告)日：2014-11-25

    申请号：US13884229

    申请日：2011-10-05

    申请人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

    发明人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

    IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/20

    CPC分类号： H01L29/7827 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7789

    摘要： It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.

    摘要翻译： 本发明的目的是提高具有开口的垂直半导体器件的击穿电压特性，并且在开口中包括由二维电子气形成的沟道。 垂直半导体器件包括具有开口28的GaN基叠层15，GaN基叠层15包括n型GaN基漂移层4 / p型GaN基阻挡层6 / n型GaN- 垂直半导体器件包括覆盖开口的再生长层27，包含电子漂移层22和电子供给层26的再生长层27，源电极S和位于 在再生长层上。 栅电极G覆盖长度对应于p型GaN基阻挡层的厚度的部分，并且终止在壁表面上的位置，该位置远离开口的底部。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100159656A1

    公开(公告)日：2010-06-24

    申请号：US12640347

    申请日：2009-12-17

    申请人： Ken Nakata ,  Seiji Yaegashi

    发明人： Ken Nakata ,  Seiji Yaegashi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7789 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7787 ,  H01L29/7788

    摘要： A method for fabricating a semiconductor device includes: forming a GaN-based semiconductor layer on a substrate; forming a gate insulating film of aluminum oxide on the GaN-based semiconductor layer at a temperature equal to or lower than 450° C.; forming a protection film on an upper surface of the gate insulating film; performing a process with an alkaline solution in a state in which the upper surface of the gate insulating film is covered with the protection film; and forming a gate electrode on the gate insulating film.

    摘要翻译： 一种制造半导体器件的方法包括：在衬底上形成GaN基半导体层; 在等于或低于450℃的温度下在GaN基半导体层上形成氧化铝的栅极绝缘膜; 在所述栅极绝缘膜的上表面上形成保护膜; 在栅极绝缘膜的上表面被保护膜覆盖的状态下用碱性溶液进行处理; 以及在所述栅极绝缘膜上形成栅电极。

    Semiconductor device and method for producing the same
    9.
    发明授权
    Semiconductor device and method for producing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08816398B2

    公开(公告)日：2014-08-26

    申请号：US13824043

    申请日：2011-07-06

    申请人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

    发明人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

    IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/15 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

    CPC分类号： H01L29/778 ,  H01L29/0696 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

    摘要： There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.

    摘要翻译： 提供了一种垂直GaN基半导体器件，其中可以使用p型GaN势垒层改善导通电阻，同时提高击穿电压特性。 半导体器件包括再生长层27，其包括位于开口28的壁表面上的沟道，其端面被覆盖的p型势垒层6，与p型势垒层接触的源极层7， 位于再生长层上的栅电极G和位于开口周围的源电极S. 在半导体器件中，源极层具有超晶格结构，该超晶格结构由包括具有比p型势垒层的晶格常数小的晶格常数的第一层（层）的层叠层和具有比p型阻挡层的晶格常数小的第二层（b层） 大于第一层的晶格常数。

    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130221434A1

    公开(公告)日：2013-08-29

    申请号：US13884229

    申请日：2011-10-05

    申请人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

    发明人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7827 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7789

    摘要： It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.

    摘要翻译： 本发明的目的是提高具有开口的垂直半导体器件的击穿电压特性，并且在开口中包括由二维电子气形成的沟道。 垂直半导体器件包括具有开口28的GaN基叠层15，GaN基叠层15包括n型GaN基漂移层4 / p型GaN基阻挡层6 / n型GaN- 垂直半导体器件包括覆盖开口的再生长层27，包含电子漂移层22和电子供给层26的再生长层27，源电极S和位于 在再生长层上。 栅电极G覆盖长度对应于p型GaN基阻挡层的厚度的部分，并且终止在壁表面上的位置，该位置远离开口的底部。