公开(公告)号：US09455212B2

公开(公告)日：2016-09-27

申请号：US13473922

申请日：2012-05-17

申请人： Hiroki Uchida ,  Takeshi Shioga ,  Shigenori Aoki ,  Susumu Ogata ,  Hideaki Nagaoka

发明人： Hiroki Uchida ,  Takeshi Shioga ,  Shigenori Aoki ,  Susumu Ogata ,  Hideaki Nagaoka

IPC分类号： F28F27/00 ,  H01L23/427 ,  F28D15/04 ,  F28D15/06 ,  H01L23/34 ,  F28D15/02

CPC分类号： H01L23/427 ,  F28D15/0266 ,  F28D15/043 ,  F28D15/06 ,  H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

摘要： A loop heat pipe system includes a loop heat pipe (LHP), a temperature sensor, a heater and a controller. The temperature sensor measures temperature of a working fluid portion of the LHP in which the working fluid has different phases depending on whether or not the LHP is in a disable status not to start up a heat transportation, in which a liquid phase of the working fluid does not exist in an evaporator of the LHP. The heater heats a heating target part of a vapor line. The controller, in order to start up the LHP, turns on the heater, monitors temperature of the heating target part using the temperature sensor, and turns off the heater when detecting a change in the monitored temperature, caused by condensation of a vapor phase of the working fluid.

摘要翻译： 回路热管系统包括回路热管（LHP），温度传感器，加热器和控制器。 温度传感器根据LHP是否处于禁止状态而测量工作流体具有不同相位的LHP的工作流体部分的温度，而不启动热运输，其中工作流体的液相 在LHP的蒸发器中不存在。 加热器加热蒸气管线的加热目标部分。 控制器为了启动LHP，打开加热器，使用温度传感器监测加热对象部件的温度，并且当检测到监测到的温度变化时，关闭加热器，该温度由蒸气相的冷凝引起 工作流体。

公开(公告)号：US20120227954A1

公开(公告)日：2012-09-13

申请号：US13473922

申请日：2012-05-17

申请人： Hiroki UCHIDA ,  Takeshi Shioga ,  Shigenori Aoki ,  Susumu Ogata ,  Hideaki Nagaoka

发明人： Hiroki UCHIDA ,  Takeshi Shioga ,  Shigenori Aoki ,  Susumu Ogata ,  Hideaki Nagaoka

IPC分类号： F28F27/00 ,  F25B29/00

CPC分类号： H01L23/427 ,  F28D15/0266 ,  F28D15/043 ,  F28D15/06 ,  H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

摘要： A loop heat pipe system includes: a loop heat pipe (LHP) including an evaporator, a condenser, a vapor line, and a liquid; a temperature sensor to measure temperature of part of the LHP, a working fluid portion in which has different phases in a situation where the LHP functions as a heat transport device and in a situation where the LHP dose not function as a heat transport device and a liquid phase of the working fluid dose not exist in the evaporator; a heater to heat a heating target part of the vapor line; and a controller, in order to start the LHP, to turn on the heater, to monitor temperature of the heating target part using the temperature sensor, and to turn off the heater when detecting a change caused by condensation of a vapor phase of the working fluid in the monitored temperature.

摘要翻译： 回路热管系统包括：包括蒸发器，冷凝器，蒸汽管线和液体的回路热管（LHP）; 用于测量LHP的一部分的温度的温度传感器，在LHP用作热传输装置的情况下以及LHP剂量不用作热输送装置的情况下具有不同相的工作流体部分 在蒸发器中不存在工作流体的液相剂量; 用于加热所述蒸气管线的加热目标部分的加热器; 以及控制器，为了启动LHP，打开加热器，使用温度传感器监测加热对象部件的温度，并且当检测到加热器的气相的冷凝所引起的变化时关闭加热器 流体在监测温度。

公开(公告)号：US06316812B1

公开(公告)日：2001-11-13

申请号：US09564669

申请日：2000-05-04

申请人： Hideaki Nagaoka

发明人： Hideaki Nagaoka

IPC分类号： H01L2976

CPC分类号： G11C5/147 ,  G11C11/412 ,  G11C11/417 ,  Y10S257/903 ,  Y10S257/904

摘要： A memory cell power supply circuit includes: a memory cell power supply PMOS transistor connected between a power supply node and a power supply potential, a diode-connected transistor provided between a gate of the memory cell power supply transistor and the power supply potential, and a resistor provided between the gate of the memory cell power supply transistor and a ground potential. During a writing operation when a value of current flowing to the memory cell is high, if the power supply potential increases, a cell power supply potential down-converted by a greater amount is supplied to the memory cell.

摘要翻译： 存储单元电源电路包括：连接在电源节点和电源电位之间的存储单元电源PMOS晶体管，设置在存储单元电源晶体管的栅极和电源电位之间的二极管连接的晶体管，以及 设置在存储单元电源晶体管的栅极和地电位之间的电阻器。 在写入操作期间当流向存储单元的电流值高时，如果电源电位增加，则向存储单元提供下降转换的单元电源电位较大量的单元电源电位。

公开(公告)号：US5973533A

公开(公告)日：1999-10-26

申请号：US016433

申请日：1998-01-30

申请人： Hideaki Nagaoka

发明人： Hideaki Nagaoka

IPC分类号： G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  H03K5/13 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0944 ,  H03K3/01

CPC分类号： H03K19/00384

摘要： In a semiconductor gate circuit, an MOS transistor having a low threshold voltage and a standard MOS transistor having threshold voltages of large absolute values are connected in series between an output node and a power supply node. The MOS transistor having the threshold voltage of the large absolute value receives on a gate thereof, a signal preceding in phase a signal applied to a gate of the MOS transistor having the small threshold voltage. In the semiconductor gate circuit, a dependency of input/output characteristics on a power supply voltage is small, and a leak current during standby is reduced. The standard MOS transistor turns on prior to turning on of the low threshold voltage MOS transistor, and turns off when the low threshold voltage MOS transistor turns off. The output node driving current is controlled by the low threshold voltage MOS transistor while a subthreshold leak current is suppressed by the standard transistor. A gate circuit having a small dependency of an input/output characteristics on the power supply voltage is implemented without increasing the power consumption.

摘要翻译： 在半导体栅极电路中，具有低阈值电压的MOS晶体管和具有大绝对值的阈值电压的标准MOS晶体管串联连接在输出节点和电源节点之间。 具有大绝对值的阈值电压的MOS晶体管在其栅极上接收信号，该信号在施加到具有小阈值电压的MOS晶体管的栅极的相位之前。 在半导体门电路中，输入/输出特性对电源电压的依赖性小，并且待机期间的泄漏电流降低。 标准MOS晶体管在低阈值电压MOS晶体管导通之前导通，当低阈值电压MOS晶体管截止时，该晶体管截止。 输出节点驱动电流由低阈值电压MOS晶体管控制，而亚阈值漏电流被标准晶体管抑制。 实现输入/输出特性对电源电压的依赖性小的门电路，而不增加功耗。

公开(公告)号：US06781917B2

公开(公告)日：2004-08-24

申请号：US10178411

申请日：2002-06-25

申请人： Hideaki Nagaoka

发明人： Hideaki Nagaoka

IPC分类号： G11C800

CPC分类号： G11C11/419 ,  G11C11/412

摘要： A semiconductor memory device is provided including plural memory cells and capable of a dual port access. In the memory device the memory cell is composed with two driver transistors 1, two load transistors 2, and two access transistors 3, and in the data read, the word line 11 makes the access transistors 3 conductive to read out data held in the driver transistors to a pair of the bit lines, and in the data write, the load transistor control line makes the load transistors conductive to write data into the driver transistors from a pair of the memory cell VCC lines.

摘要翻译： 提供了包括多个存储单元并能够进行双端口访问的半导体存储器件。 在存储器件中，存储器单元由两个驱动晶体管1，两个负载晶体管2和两个存取晶体管3组成，并且在数据读取中，字线11使得存取晶体管3导通以读出保持在驱动器中的数据 晶体管到一对位线，并且在数据写入中，负载晶体管控制线使得负载晶体管导通，从一对存储单元VCC线将数据写入驱动器晶体管。

公开(公告)号：US5973984A

公开(公告)日：1999-10-26

申请号：US61055

申请日：1998-04-16

申请人： Hideaki Nagaoka

发明人： Hideaki Nagaoka

IPC分类号： G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C16/04 ,  G11C8/00 ,  G11C11/00

CPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419

摘要： Memory blocks having word lines driven into selected states independently of each other are provided in correspondence to data input/output bits respectively. Each memory cell includes a bipolar transistor and a MOS transistor. In each memory block, a current flows to a bit line only of a selected column, and a 1-bit memory cell is accessed therein. Thus, sense amplifiers and write drivers have only to be provided in numbers corresponding to that of the data bits, whereby the circuit occupying area as well as current consumption are reduced.

摘要翻译： 分别对应于数据输入/输出位提供具有彼此独立地驱动到选定状态的字线的存储块。 每个存储单元包括双极晶体管和MOS晶体管。 在每个存储器块中，电流仅流向选定列的位线，并且在其中访问1位存储器单元。 因此，读出放大器和写入驱动器的数量只能与数据位的数量相对应，从而减少了电路占用面积和电流消耗。

公开(公告)号：US06400597B1

公开(公告)日：2002-06-04

申请号：US09760802

申请日：2001-01-17

申请人： Hideaki Nagaoka

发明人： Hideaki Nagaoka

IPC分类号： G11C506

CPC分类号： G11C8/12

摘要： The number of apparently independently operating memory sets can be changed by providing the same number of address setting circuits as that of memory cell arrays. Since the number of mounted address setting circuits increases compared with a case where the number of memory sets is fixed, the problem arises that the layout area in a semiconductor memory device increases. However, by providing a switching circuit for switching the correspondence relationship between memory cell arrays and address setting circuits in response to a signal selecting the number of memory sets, a semiconductor memory device capable of changing the number of memory sets which seemingly independently operate without providing the same number of address setting circuits as that of memory cell arrays.

公开(公告)号：US06396123B1

公开(公告)日：2002-05-28

申请号：US09548617

申请日：2000-04-13

申请人： Hideaki Nagaoka

发明人： Hideaki Nagaoka

IPC分类号： H01L2900

CPC分类号： H01L29/66189 ,  H01L21/31053 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A dummy pattern for use in a chemical mechanical polishing (CMP) process is disposed in a field dummy region within a p− well region, isolated by an isolating insulating film, wherein the p− well region has a potential fixed by a ground electrode. The dummy pattern includes a gate insulating film dummy pattern and a gate electrode dummy pattern, formed in the same layers as a gate insulating film and a gate electrode, respectively, of an NMOS transistor. The gate electrode dummy pattern is connected with a contact plug, which in turn is connected with a power supply electrode (Vcc) interconnection line. Thus, a decoupling condenser, formed of the field dummy region within the p− well, the gate insulating film dummy pattern and the gate electrode dummy pattern by utilizing the dummy patterns for use in the CMP process, is connected in parallel with a primary electronic circuit. As a result, a semiconductor device is obtained which operates at a low voltage with suppressed electromagnetic interference (EMI), without increasing an area occupied by the semiconductor device.

摘要翻译： 在化学机械抛光（CMP）工艺中使用的虚拟图案设置在p-阱区域内的场模拟区域中，通过隔离绝缘膜隔离，其中p阱区域具有由接地电极固定的电位。 虚设图形包括分别与NMOS晶体管的栅极绝缘膜和栅极电极相同的层形成的栅极绝缘膜虚设图形和栅极虚拟图案。 栅电极虚设图案与接触插头连接，接触插头又与电源电极（Vcc）互连线连接。 因此，通过利用在CMP工艺中使用的虚拟图案，由p阱内的场模拟区域形成的去耦电容器，栅极绝缘膜虚设图形和栅电极虚拟图案与主电子 电路。 结果，获得了在抑制电磁干扰（EMI）的情况下以低电压工作的半导体器件，而不增加半导体器件占据的面积。

公开(公告)号：US06333877B1

公开(公告)日：2001-12-25

申请号：US09606316

申请日：2000-06-29

申请人： Hideaki Nagaoka ,  Kiyoyasu Akai

发明人： Hideaki Nagaoka ,  Kiyoyasu Akai

IPC分类号： G11C700

CPC分类号： G11C29/70

摘要： A memory cell power supply line is provided to supply a ground potential corresponding to each column in a regular memory cell array. Among fuse elements, the fuse element corresponding to the memory cell column that is to be subjected to redundancy replacement is decoupled, whereby supply of the ground potential to the regular memory cell column to be replaced is suppressed.

摘要翻译： 存储单元电源线被提供以在常规存储单元阵列中提供对应于每列的接地电位。 在熔丝元件中，对应于要进行冗余替换的存储单元列的熔丝元件被去耦合，由此抑制要被替换的常规存储单元列的接地电位的供应。

公开(公告)号：US06307772B1

公开(公告)日：2001-10-23

申请号：US09546710

申请日：2000-04-10

申请人： Hideaki Nagaoka

发明人： Hideaki Nagaoka

IPC分类号： G11C1100

CPC分类号： G11C11/419

摘要： In an SRAM, a breaking circuit includes a P channel MOS transistor connected between the source of an N channel MOS transistor, which forms a bit line load, and one end of a bit line, and an inverter to supply the gate of the P channel MOS transistor with an inverted signal of a signal which appears at the one end of the bit line. If the bit line is short-circuited with a line of a ground potential and is defective, the P channel MOS transistor is rendered non-conductive, thereby preventing current leakage from a line of a power supply potential through the defective bit line to the ground potential line. Therefore, current consumption is reduced.

摘要翻译： 在SRAM中，分断电路包括连接在形成位线负载的N沟道MOS晶体管的源极和位线的一端之间的P沟道MOS晶体管，以及提供P沟道的栅极的反相器 MOS晶体管具有出现在位线一端的信号的反相信号。 如果位线与地电位线短路并且有故障，则P沟道MOS晶体管变得不导通，从而防止从通过缺陷位线到地的电源电位线的电流泄漏 潜力线。 因此，电流消耗减少。