公开(公告)号：US20060050820A1

公开(公告)日：2006-03-09

申请号：US10539235

申请日：2004-02-10

申请人： Hirotsugu Kawada ,  Yoshiyuki Saito ,  Osamu Shibata ,  Hiroshi Suenaga ,  Takahisa Sakai ,  Toshitomo Umei ,  Takashi Akita ,  Yuji Mizuguchi ,  Noboru Katta

发明人： Hirotsugu Kawada ,  Yoshiyuki Saito ,  Osamu Shibata ,  Hiroshi Suenaga ,  Takahisa Sakai ,  Toshitomo Umei ,  Takashi Akita ,  Yuji Mizuguchi ,  Noboru Katta

IPC分类号： H04L7/00

CPC分类号： H04L7/00 ,  H04L7/0334

摘要： A signal receiver (11) receives an analog signal via a twisted pair cable (31). An A/D converter (12) converts the analog signal to a digital signal. A phase detection unit (14) detects the phase of the digital signal, and generates a reception timing signal. A transmission timing generation unit (15) controls, based on the reception timing signal, timing for a transmission processing unit (16) to output the digital signal such that the reception signal (point A) and a transmission signal (point D) are different in phase by a predetermined degree. The transmission processing unit (16) outputs, in accordance with the timing, a digital signal obtained by performing mapping on data inputted from a connection device (20). A D/A converter (17) converts the digital signal to an analog signal. A signal transmitter (18) transmits the analog signal via a twisted pair cable (32).

摘要翻译： 信号接收器（11）经由双绞线电缆（31）接收模拟信号。 A / D转换器（12）将模拟信号转换成数字信号。 相位检测单元（14）检测数字信号的相位，并产生接收定时信号。 发送定时生成单元（15）基于接收定时信号，控制发送处理单元（16）输出数字信号的定时，使得接收信号（点A）和发送信号（点D）不同 同时预定的程度。 发送处理单元（16）根据定时输出通过对从连接装置（20）输入的数据进行映射而获得的数字信号。 D / A转换器（17）将数字信号转换成模拟信号。 信号发送器（18）经由双绞线电缆（32）发送模拟信号。

公开(公告)号：US20070252659A1

公开(公告)日：2007-11-01

申请号：US11664129

申请日：2005-08-01

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Noboru Katta ,  Yuji Mizuguchi

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Noboru Katta ,  Yuji Mizuguchi

IPC分类号： H03H7/38

CPC分类号： H01F17/0013 ,  H01F2017/0093 ,  H03H7/09 ,  H03H7/427 ,  H03H2001/0085 ,  H04B3/30 ,  H04L12/40032 ,  H04L2012/40215 ,  H04L2012/4026

摘要： In a filter circuit (1), a common mode choke (2) and a normal mode choke (3) have extremely high and low impedances, respectively, for common mode signals received through two input terminals (1a and 1b). The chokes have the opposite impedance characteristics for differential signals. In particular, the difference in impedance is large. Furthermore, the normal mode choke (3) is installed as a previous stage of the common mode choke (2). Accordingly, common mode noises which enter the two input terminals (1a and 1b) penetrate the normal mode choke (3), but neither penetrate the common mode choke (2) nor are reflected from the common mode choke (2). In particular, common mode currents flow through the normal mode choke (3) but do not flow through the common mode choke (2).

摘要翻译： 在滤波器电路（1）中，对于通过两个输入端子（1a和1b）接收的共模信号，共模扼流圈（2）和正常模式扼流圈（3）分别具有极高和低阻抗。 扼流圈对差分信号具有相反的阻抗特性。 特别地，阻抗的差异很大。 此外，正常模式扼流圈（3）安装为共模扼流圈（2）的前一级。 因此，进入两个输入端子（1a和1b）的共模噪声穿透正常模式扼流圈（3），但都不穿透共模扼流圈（2），也不会从共模扼流圈（2）反射。 特别地，共模电流流过正常模式扼流圈（3），但不流过共模扼流圈（2）。

公开(公告)号：US07886085B2

公开(公告)日：2011-02-08

申请号：US12295051

申请日：2007-02-20

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Noriaki Takeda ,  Toru Iwata ,  Takaharu Yoshida ,  Yoshiyuki Saito

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Noriaki Takeda ,  Toru Iwata ,  Takaharu Yoshida ,  Yoshiyuki Saito

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： H04L7/10 ,  G06F1/12 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/044 ,  H04L7/046

摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.

摘要翻译： 本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。 一种向主机终端发送/接收数据的可移动存储装置，包括：接收用于在主机终端和可移动存储装置之间发送/接收数据的发送/接收时钟的时钟接收部分， 主机终端; 相位同步模式生成部，其基于所述发送接收时钟生成相位同步模式，所述相位同步模式用于调整所述主机终端结合的用于从所述可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将所生成的相位同步模式发送到所述主机终端，并且所述相位同步模式包括持续至少两个周期的第一电平信号，以及在所述第一电平信号之后持续的第二电平信号， 提供一个循环。

公开(公告)号：US20100289534A1

公开(公告)日：2010-11-18

申请号：US12847161

申请日：2010-07-30

申请人： Hiroshi SUENAGA ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi SUENAGA ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03B1/00

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US20090290582A1

公开(公告)日：2009-11-26

申请号：US12295407

申请日：2007-02-20

申请人： Hiroshi Suenaga. ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Noriaki Takeda ,  Takaharu Yoshida

发明人： Hiroshi Suenaga. ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Noriaki Takeda ,  Takaharu Yoshida

IPC分类号： H04L12/56 ,  H04J3/00

CPC分类号： H04L25/14

摘要： It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.

摘要翻译： 本发明的一个目的是抑制由于中断信号的传输引起的数据传输效率的下降。 本发明提供了一种信号传输方法，其特征在于，接收侧和发送侧将数据划分成多个数据片段，并通过至少两条传输线发送和接收多个数据片段，其中发送侧首先发送 在传输线的第一传输线上的多个数据片段的数据片段，通过第二传输线传输包括标题信息的数据包，具有与第一数据片段相同的位长的第二数据片段，以及页脚信息 除了第一传输线之外，并且同步地发送第一数据片段和第二数据片段，并且用于控制发送侧的中断信号在作为间隔的时隙中的从接收侧发送到发送侧 在第一传输线上相邻的第一数据片段之间。

公开(公告)号：US20090290274A1

公开(公告)日：2009-11-26

申请号：US12468475

申请日：2009-05-19

申请人： Hiroshi SUENAGA ,  Yoshiyuki Saito ,  Osamu Shibata ,  Yukihiro Fukumoto

发明人： Hiroshi SUENAGA ,  Yoshiyuki Saito ,  Osamu Shibata ,  Yukihiro Fukumoto

IPC分类号： H02H9/04 ,  H05K1/02

CPC分类号： G06K19/07743 ,  G06K19/07732 ,  G06K19/07735 ,  H01L2224/16225 ,  H05K1/0237 ,  H05K1/0259 ,  H05K1/112 ,  H05K1/117 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10159 ,  H05K2201/10174 ,  H05K2201/10674

摘要： According to the present invention, the setting height position of a first terminal is set to be lower than the setting height position of a second terminal on the terminal formation surface of a printed substrate, so that the protection of an internal circuit and the transmission of a high-speed signal can be both achieved.

摘要翻译： 根据本发明，第一端子的设定高度位置被设定为低于印刷基板的端子形成面上的第二端子的设定高度位置，使得内部电路的保护和传输 可以实现高速信号。

公开(公告)号：US20090233489A1

公开(公告)日：2009-09-17

申请号：US12402016

申请日：2009-03-11

申请人： Osamu Shibata ,  Hiroshi Suenaga ,  Yoshiyuki Saito

发明人： Osamu Shibata ,  Hiroshi Suenaga ,  Yoshiyuki Saito

IPC分类号： H01R24/00

CPC分类号： G06F13/1689

摘要： A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.

摘要翻译： 卡控制器通过插座从记录卡接收数据。 在主发送配线中发送读时钟，在数据发送配线中发送数据。 读出时钟通过输出的传输线从卡控制器中取出，并通过输入的传输线被取回到卡控制器中。 输出发送线路的发送延迟量与主发送配线的发送延迟量相同，输入发送配线的发送延迟量与数据发送配线的发送延迟量相同。 卡控制器与由输入的传输线路检索的读取时钟同步地接收数据。

公开(公告)号：US07385466B2

公开(公告)日：2008-06-10

申请号：US11085078

申请日：2005-03-22

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito

IPC分类号： H03H7/00 ,  H04B3/28

CPC分类号： H01F17/06 ,  H01F2017/0093 ,  H01F2017/067 ,  H04L25/0272

摘要： A first transmission line for transmitting a first signal and a second transmission line for transmitting a second signal, which has the reverse phase of the first signal, are connected in series with a common mode choke coil. A third transmission line and fourth transmission line are each connected in series with the common mode choke coil, and transmit the first and second signals. A semiconductor device is connected in series with the third and fourth transmission lines, so as to transmit and receive the first and second signals. One end of a first terminator is connected in parallel with the first transmission line, and the other end is connected to the common mode choke coil. One end of a second terminator is connected in parallel with the second transmission line, and the other end is connected to the common mode choke coil. The noise eliminating capability of the common mode choke coil is increased by means of this structure.

摘要翻译： 用于发送第一信号的第一传输线和用于发送具有第一信号的相反相位的第二信号的第二传输线与共模扼流线圈串联连接。 第三传输线和第四传输线各自与共模扼流线圈串联连接，并发送第一和第二信号。 半导体器件与第三和第四传输线串联连接，以便发送和接收第一和第二信号。 第一终端器的一端与第一传输线并联连接，另一端连接到共模扼流线圈。 第二终端器的一端与第二传输线并联连接，另一端连接到共模扼流线圈。 通过这种结构，增加了共模扼流线圈的噪声消除能力。

公开(公告)号：US20120021640A1

公开(公告)日：2012-01-26

申请号：US13257560

申请日：2010-04-26

申请人： Kohei Masuda ,  Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito

发明人： Kohei Masuda ,  Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito

IPC分类号： H01R11/00

CPC分类号： H04L25/0272

摘要： A serial-parallel conversion circuit provided on one end of a cable body converts a first serial signal into parallel signals and outputs the parallel signals to parallel signal lines. A parallel-serial conversion circuit provided on another end of the cable body converts the parallel signals inputted from the parallel signal lines into a second serial signal and outputs the second serial signal to outside.

摘要翻译： 设置在电缆体的一端的串行并行转换电路将第一串行信号转换为并行信号，并将并行信号输出到并行信号线。 在电缆体的另一端设置并行转换电路，将从并行信号线输入的并行信号变换为第二串行信号，并将第二串行信号输出到外部。

公开(公告)号：US07899960B2

公开(公告)日：2011-03-01

申请号：US12402016

申请日：2009-03-11

申请人： Osamu Shibata ,  Hiroshi Suenaga ,  Yoshiyuki Saito

发明人： Osamu Shibata ,  Hiroshi Suenaga ,  Yoshiyuki Saito

IPC分类号： G06F13/12 ,  G06F13/38

CPC分类号： G06F13/1689

摘要： A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.

摘要翻译： 卡控制器通过插座从记录卡接收数据。 在主发送配线中发送读时钟，在数据发送配线中发送数据。 读出时钟通过输出的传输线从卡控制器中取出，并通过输入的传输线被取回到卡控制器中。 输出发送线路的发送延迟量与主发送配线的发送延迟量相同，输入发送配线的发送延迟量与数据发送配线的发送延迟量相同。 卡控制器与由输入的传输线路检索的读取时钟同步地接收数据。