-
1.发明授权公开(公告)号：US07777227B2
公开(公告)日：2010-08-17
申请号：US11834886
申请日：2007-08-07
申请人： Hiroshi Watanabe , Fumitaka Arai
发明人： Hiroshi Watanabe , Fumitaka Arai
IPC分类号： H01L29/04
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/456 , H01L29/66825 , H01L29/78621 , H01L29/78627 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer.
摘要翻译： 非易失性半导体存储装置包括基板，形成在基板上的第一绝缘层，在第一绝缘层上由多晶硅形成的半导体层，形成在第一绝缘层上以穿过半导体层的一对导体区域，以及 夹在半导体层的一部分上，由金属或硅化物形成，形成在夹在一对导体区域之间的半导体层的一部分上的隧道层，形成在隧道层上的电荷存储层，第二绝缘层 形成在电荷存储层上的层，以及形成在第二绝缘层上的控制栅极。
-
2.发明申请公开(公告)号：US20080111178A1
公开(公告)日：2008-05-15
申请号：US11835694
申请日：2007-08-08
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
-
公开(公告)号：US20070138536A1
公开(公告)日：2007-06-21
申请号：US11609614
申请日：2006-12-12
申请人： Fumitaka ARAI , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
发明人： Fumitaka ARAI , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.
摘要翻译： NAND单元单元在第一导电类型的半导体层上形成有先进的栅极形成工艺，该第一导电类型的半导体层形成在第一导电类型的半导体衬底上，绝缘膜插入其间。 第一导电类型的第一杂质掺杂层形成在用作选择栅晶体管的沟道区的半导体层上。第一导电类型的位线接触和源极接触用第二杂质掺杂层形成在 位线和源极线接触部分，其侧壁被绝缘膜覆盖。
-
公开(公告)号：US07393748B2
公开(公告)日：2008-07-01
申请号：US11609614
申请日：2006-12-12
申请人： Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
发明人： Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
IPC分类号： H01L21/33
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.
摘要翻译： NAND单元单元在第一导电类型的半导体层上形成有先进的栅极形成工艺，该第一导电类型的半导体层形成在第一导电类型的半导体衬底上，绝缘膜插入其间。 第一导电类型的第一杂质掺杂层形成在用作选择栅晶体管的沟道区的半导体层上。第一导电类型的位线接触和源极接触用第二杂质掺杂层形成在 位线和源极线接触部分，其侧壁被绝缘膜覆盖。
-
5.发明授权公开(公告)号：US08710573B2
公开(公告)日：2014-04-29
申请号：US12831323
申请日：2010-07-07
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
-
6.发明申请公开(公告)号：US20100270607A1
公开(公告)日：2010-10-28
申请号：US12831323
申请日：2010-07-07
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
-
7.发明授权公开(公告)号：US07777270B2
公开(公告)日：2010-08-17
申请号：US11835694
申请日：2007-08-08
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
-
8.发明申请公开(公告)号：US20080283839A1
公开(公告)日：2008-11-20
申请号：US11834886
申请日：2007-08-07
申请人： Hiroshi Watanabe , Fumitaka Arai
发明人： Hiroshi Watanabe , Fumitaka Arai
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/456 , H01L29/66825 , H01L29/78621 , H01L29/78627 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer.
摘要翻译： 非易失性半导体存储装置包括基板，形成在基板上的第一绝缘层，在第一绝缘层上由多晶硅形成的半导体层，形成在第一绝缘层上以穿过半导体层的一对导体区域，以及 夹在半导体层的一部分上，由金属或硅化物形成，形成在夹在一对导体区域之间的半导体层的一部分上的隧道层，形成在隧道层上的电荷存储层，第二绝缘层 形成在电荷存储层上的层，以及形成在第二绝缘层上的控制栅极。
-
公开(公告)号：US20190114273A1
公开(公告)日：2019-04-18
申请号：US16218600
申请日：2018-12-13
申请人： Hiroshi Watanabe
发明人： Hiroshi Watanabe
IPC分类号： G06F13/20 , G06F13/16 , H04L29/06 , H04L9/32 , H04L9/06 , H01L29/861 , H01L29/788 , H01L29/78 , H01L49/02 , H01L27/112 , H01L27/06 , H01L23/525 , H01L23/522 , H01L23/528 , G06F21/73 , G06F21/44 , G06F13/40
CPC分类号： G06F13/20 , G06F13/1673 , G06F13/4068 , G06F21/44 , G06F21/73 , H01L23/5226 , H01L23/5256 , H01L23/528 , H01L27/0629 , H01L27/11286 , H01L28/60 , H01L29/78 , H01L29/7883 , H01L29/861 , H04L9/0662 , H04L9/3278 , H04L63/083 , H04L63/0876
摘要： A method of using a chip identification device is jointly performed by a chip mass-produced by a semiconductor manufacturing process, a first chip manufacturer making the chip, and a chip user assembling a product by using the chip. The method includes inputting a first published passcode, published by the first chip manufacturer, inputting a second published passcode published by a second chip manufacturer, inputting the first published passcode to the chip by the chip user, reading an aggregate of electronic output signals as a read code, sending the read code to the first chip manufacturer to compare the first output code and the read code. The chip is regarded as a counterfeit if the comparison is consistent.
-
公开(公告)号：US09894095B2
公开(公告)日：2018-02-13
申请号：US15064693
申请日：2016-03-09
申请人： Hiroshi Watanabe
发明人： Hiroshi Watanabe
IPC分类号： H04L9/32 , H04L29/06 , G06F21/73 , G09C1/00 , G06F21/44 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/34 , H01L21/02 , H01L23/528
CPC分类号： H04L63/1441 , G06F21/44 , G06F21/73 , G06F2221/2129 , G09C1/00 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/34 , H01L21/02236 , H01L21/02255 , H01L23/528 , H04L9/3278 , H04L63/083 , H04L65/1073
摘要： A technology precluding attacks through peripheral devices thefts to a network of electronic appliance, by utilizing physical chip identification devices, is disclosed. The electronic appliance in the network are divided into the peripheral devices and stem servers managing registration information of the peripheral devices, wherein the stem servers serve as central control using software, and the peripheral devices are managed at device-level by having physical chip identification devices, thus the security of the whole network is efficiently reinforced.
-
-
-
-
-
-
-
-
-
搜索结果
841 条记录 (耗时 0.026 秒)
