公开(公告)号：US20070121273A1

公开(公告)日：2007-05-31

申请号：US11601760

申请日：2006-11-20

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

IPC分类号： H01G4/228

CPC分类号： H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

摘要翻译： 为了提供能够防止电容器未对准的内置电容器型布线板，提供了一种电容器内置型布线板，其包括芯板; 多层部分，设置在所述芯板的至少一侧上，并由多个层间绝缘层形成; 以及在芯板上交替层叠的多个导体层。 电容器是具有第一和第二主表面的芯片状形状并且包括电介质层; 层压在电介质层上的电极层; 以及至少在所述第二主表面处开口的孔部分。 电容器嵌入在层间绝缘层中，使得第二主表面面向芯板。

公开(公告)号：US07532453B2

公开(公告)日：2009-05-12

申请号：US11601760

申请日：2006-11-20

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

IPC分类号： H01G4/228

CPC分类号： H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

摘要翻译： 为了提供能够防止电容器未对准的内置电容器型布线板，提供了一种电容器内置型布线板，其包括芯板; 多层部分，设置在所述芯板的至少一侧上，并由多个层间绝缘层形成; 以及在芯板上交替层叠的多个导体层。 电容器是具有第一和第二主表面的芯片状形状并且包括电介质层; 层压在电介质层上的电极层; 以及至少在所述第二主表面处开口的孔部分。 电容器嵌入在层间绝缘层中，使得第二主表面面向芯板。

公开(公告)号：US07932471B2

公开(公告)日：2011-04-26

申请号：US11498785

申请日：2006-08-04

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC分类号： H05K1/16

CPC分类号： H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

摘要翻译： 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US20070117338A1

公开(公告)日：2007-05-24

申请号：US11603161

申请日：2006-11-22

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

IPC分类号： H01L21/20 ,  H01L29/00

CPC分类号： H05K1/186 ,  H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00

摘要： A via array capacitor comprising: a capacitor body including a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total of a thickness of the metal-containing layers disposed on the first main surface and a thickness of the metal-containing layers disposed on the second main surface is from 15% to 80% of an overall thickness of the via array capacitor.

摘要翻译： 一种通孔阵列电容器，包括：电容器主体，包括第一主表面和第二主表面，并且具有交替层叠电介质层和内电极层的结构; 多个通孔导体，其将内部电极层彼此导引并且整体上排列成阵列形式; 和设置在第一主表面和第二主表面中的至少一个上的含金属层，其中设置在第一主表面上的含金属层的厚度和含金属层的厚度的总和 设置在第二主表面上的通孔阵列电容器的总厚度的15％至80％。

公开(公告)号：US20070030628A1

公开(公告)日：2007-02-08

申请号：US11498785

申请日：2006-08-04

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC分类号： H01G4/06

CPC分类号： H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

摘要翻译： 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US08546700B2

公开(公告)日：2013-10-01

申请号：US13042686

申请日：2011-03-08

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC分类号： H05K1/16

CPC分类号： H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

摘要翻译： 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US20110157763A1

公开(公告)日：2011-06-30

申请号：US13042686

申请日：2011-03-08

申请人： Hiroshi YAMAMOTO ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

发明人： Hiroshi YAMAMOTO ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC分类号： H01G4/224 ,  H01G4/30

CPC分类号： H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

摘要翻译： 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US07580240B2

公开(公告)日：2009-08-25

申请号：US11603161

申请日：2006-11-22

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

IPC分类号： H01G4/06 ,  H01G4/228

CPC分类号： H05K1/186 ,  H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00

摘要： A via array capacitor including a capacitor body having a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total volume of the inner electrode layers and the metal-containing layers included in the via array capacitor is from 45 vol.% to 95 vol.% of a volume of the via array capacitor.

摘要翻译： 一种通孔阵列电容器，包括具有第一主表面和第二主表面的电容器体，并且具有其中电介质层和内电极层交替层叠的结构; 多个通孔导体，其将内部电极层彼此导引并且整体上排列成阵列形式; 和设置在第一主表面和第二主表面中的至少一个上的含金属层，其中包含在通孔阵列电容器中的内部电极层和含金属层的总体积为45体积％ 至95体积％的通孔阵列电容器的体积。

公开(公告)号：US20070045814A1

公开(公告)日：2007-03-01

申请号：US11508968

申请日：2006-08-24

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

IPC分类号： H01L23/04

CPC分类号： H01L21/6835 ,  H01G4/236 ,  H01G4/30 ,  H01L21/568 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

摘要翻译： 布线基板包括嵌入其中的基板芯和陶瓷芯片。 基板芯具有在芯主表面处开口的壳体开口部。 陶瓷芯片容纳在壳体开口部分中，使得芯主表面和芯片第一主表面相同。 陶瓷芯片包括多个由金属化层构成的第二端子电极，并且形成在芯片第二主表面上以从其突出。 在芯片第二主表面上形成有从第二主表面侧配置成包围多个第二端子电极的突出部，从而突出。

公开(公告)号：US20060175083A1

公开(公告)日：2006-08-10

申请号：US11350285

申请日：2006-02-09

申请人： Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

发明人： Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

IPC分类号： H05K1/16

CPC分类号： H01G2/06 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.

摘要翻译： 中间板具有由主芯体和副芯部形成的板芯。 主芯体具有板状形状，并且包括其中容纳有副芯部的开放子芯容纳部。 板芯的第一端子阵列具有与子芯部的正交突起重叠的区域。 后者包括由其间具有陶瓷（电介质）层的第一和第二导体层形成的层叠陶瓷电容器。 第一层连接到第一类型的第一和第二侧端子，而第二层连接到第二类型的第一和第二侧端子。 壳体部分具有横截面为正方形的内边缘，并且在每个拐角处形成具有0.1至2mm的尺寸的半径部分。