公开(公告)号：US20100203231A1

公开(公告)日：2010-08-12

申请号：US12531363

申请日：2008-03-28

申请人： Hiroyuki Kusaka ,  Koji Kuromiya ,  Satoshi Saito ,  Takashi Shigematsu ,  Akihiro Murakami ,  Shinji Ichikawa ,  Haruo Sakuma ,  Shingo Nishijima

发明人： Hiroyuki Kusaka ,  Koji Kuromiya ,  Satoshi Saito ,  Takashi Shigematsu ,  Akihiro Murakami ,  Shinji Ichikawa ,  Haruo Sakuma ,  Shingo Nishijima

IPC分类号： B05D5/12 ,  B05C9/14 ,  B05C9/12 ,  B05C11/00

CPC分类号： H01B13/14 ,  H01B3/301

摘要： Disclosed is a method of producing an insulated electric wire, in which a primary coating layer including at least an enamel-baking layer is formed on a metallic conductor to form a primary coated electric wire, and a secondary coating layer is extrusion-formed on the primary coating layer of the primary coated electric wire. The method includes an electric wire pre-heating process where a surface of the primary coating layer is pre-heated using an electric wire pre-heating unit, and a resin extrusion process where a secondary coating layer is extrusion-formed on the pre-heated primary coating layer using a resin extrusion unit. Further disclosed is an apparatus for producing an insulated electric wire.

摘要翻译： 公开了一种制造绝缘电线的方法，其中在金属导体上形成至少包含搪瓷烘烤层的初级涂层以形成初级涂覆电线，并且在第二涂层上挤出形成第二涂层 初级涂层电线的主要涂层。 该方法包括电线预热工艺，其中使用电线预热单元对初级涂层的表面进行预热，以及树脂挤出方法，其中将二次涂层挤压形成在预热 初级涂层使用树脂挤出单元。 另外公开了一种绝缘电线的制造装置。

公开(公告)号：US08790747B2

公开(公告)日：2014-07-29

申请号：US12531363

申请日：2008-03-28

申请人： Hiroyuki Kusaka ,  Koji Kuromiya ,  Satoshi Saito ,  Takashi Shigematsu ,  Akihiro Murakami ,  Shinji Ichikawa ,  Haruo Sakuma ,  Shingo Nishijima

发明人： Hiroyuki Kusaka ,  Koji Kuromiya ,  Satoshi Saito ,  Takashi Shigematsu ,  Akihiro Murakami ,  Shinji Ichikawa ,  Haruo Sakuma ,  Shingo Nishijima

IPC分类号： H01B13/06

CPC分类号： H01B13/14 ,  H01B3/301

摘要： Disclosed is a method of producing an insulated electric wire, in which a primary coating layer including at least an enamel-baking layer is formed on a metallic conductor to form a primary coated electric wire, and a secondary coating layer is extrusion-formed on the primary coating layer of the primary coated electric wire. The method includes an electric wire pre-heating process where a surface of the primary coating layer is pre-heated using an electric wire pre-heating unit, and a resin extrusion process where a secondary coating layer is extrusion-formed on the pre-heated primary coating layer using a resin extrusion unit. Further disclosed is an apparatus for producing an insulated electric wire.

摘要翻译： 公开了一种制造绝缘电线的方法，其中在金属导体上形成至少包含搪瓷烘烤层的初级涂层以形成初级涂覆电线，并且在第二涂层上挤出形成第二涂层 初级涂层电线的主要涂层。 该方法包括电线预热工艺，其中使用电线预热单元对初级涂层的表面进行预热，以及树脂挤出方法，其中将二次涂层挤压形成在预热 初级涂层使用树脂挤出单元。 另外公开了一种绝缘电线的制造装置。

公开(公告)号：US20070278567A1

公开(公告)日：2007-12-06

申请号：US11882626

申请日：2007-08-03

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L29/78

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

公开(公告)号：US06767196B2

公开(公告)日：2004-07-27

申请号：US10055023

申请日：2002-01-22

申请人： Jun Yamakawa ,  Masahiro Hirao ,  Yasushi Kihara ,  Takashi Shigematsu

发明人： Jun Yamakawa ,  Masahiro Hirao ,  Yasushi Kihara ,  Takashi Shigematsu

IPC分类号： B29C4516

CPC分类号： B29C45/14549 ,  B29C45/261 ,  B29L2011/0075

摘要： A manufacturing apparatus for multi-fiber optical ferrule includes a spacer whose hardness is equivalent to or higher than the hardness of pins for forming fiber holes. Further, corner portions with respect to the arrangement direction of the pins for forming fiber holes of the spacer are formed as inclined surfaces or rounded surfaces.

摘要翻译： 多纤维光学套管的制造装置包括硬度等于或高于用于形成纤维孔的销的硬度的间隔件。 此外，相对于用于形成间隔件的纤维孔的销的排列方向的角部形成为倾斜表面或圆形表面。

公开(公告)号：US5706378A

公开(公告)日：1998-01-06

申请号：US626946

申请日：1996-04-03

申请人： Kenji Suzuki ,  Takashi Shigematsu

发明人： Kenji Suzuki ,  Takashi Shigematsu

IPC分类号： G02B6/30

CPC分类号： G02B6/30

摘要： An optical waveguide chip assembly in which a plurality of optical waveguide patterns and two positioning grooves are laterally arranged is prepared by forming a plurality of optical waveguide patterns and two positioning grooves on a wafer in parallel to each other and cutting the wafer. Separately from this, an optical fiber array assembly having a plurality of optical fiber array cables and two guide pin holes is prepared. The optical waveguide chip assembly and the optical fiber array assembly are joined while aligning by the guide pins and then divided into units of individual optical waveguide modules. A large number of optical waveguide modules can be made with a good efficiency, and the mass productivity is improved. Since a plurality of optical waveguide modules are made by the same positioning, variations among products can be reduced.

摘要翻译： 通过在晶片上形成多个光波导图案和两个定位槽，并且切割晶片来制备多个光波导图案和两个定位槽横向布置的光波导芯片组件。 另外，准备具有多个光纤阵列电缆和两个导销孔的光纤阵列组件。 光波导芯片组件和光纤阵列组件通过导销对准而接合，然后分成各个光波导模块的单元。 可以以高效率制造大量的光波导模块，并且提高了批量生产率。 由于通过相同的定位制造多个光波导模块，因此可以降低产品之间的差异。

公开(公告)号：US5548675A

公开(公告)日：1996-08-20

申请号：US335769

申请日：1994-11-08

申请人： Takashi Shigematsu ,  Hisaharu Yanagawa ,  Takeo Shimizu ,  Shiro Nakamura ,  Kazuya Fukasawa ,  Tomohiro Watanabe

发明人： Takashi Shigematsu ,  Hisaharu Yanagawa ,  Takeo Shimizu ,  Shiro Nakamura ,  Kazuya Fukasawa ,  Tomohiro Watanabe

IPC分类号： G02B6/30 ,  G02B6/38 ,  G02B6/42 ,  G02B6/00 ,  G02B6/36

CPC分类号： G02B6/4249 ,  G02B6/30 ,  G02B6/3865 ,  G02B6/3834 ,  G02B6/4237

摘要： An optical fiber end portion (10) which has a ferrule (11) which comprises a butting end face (11e) opposed to or butted against an optical device (20), and a single fiber hole or a plurality of fiber holes formed in parallel at predetermined intervals, into which one end of optical fiber (13a) is inserted, the optical fiber being optically connected to said optical device, a method for manufacturing the optical fiber end portion, and a construction for connecting the end portion to the optical device. The ferrule is formed of a molded product of synthetic resin, and is provided with at least one connecting member (12) on the side of butting end face connected to the optical device. The connecting member (12) has a linear expansion coefficient set at a value smaller than the linear expansion coefficient of a synthetic resin forming the ferrule.

摘要翻译： PCT No.PCT / JP94 / 00536 Sec。 371日期：1994年11月8日 102（e）1994年11月8日日期PCT 1994年3月31日PCT公布。 公开号WO94 / 23321 日期：1994年10月13日具有套圈（11）的光纤端部（10），其包括与光学元件（20）相对或对接的对接端面（11e），以及单个光纤孔 以预定间隔平行地形成的光纤孔，光纤（13a）的一端插入其中，光纤与所述光学装置光学连接，制造光纤端部的方法和用于连接端部的结构 部分到光学装置。 套圈由合成树脂的模制产品形成，并且在与光学装置连接的对接端面的侧面上设置有至少一个连接构件（12）。 连接构件（12）的线膨胀系数设定为小于形成套圈的合成树脂的线膨胀系数的值。

公开(公告)号：US5269998A

公开(公告)日：1993-12-14

申请号：US887012

申请日：1992-05-22

申请人： Koichi Takagi ,  Takashi Shigematsu ,  Takahide Kimura ,  Seiichi Imamizo

发明人： Koichi Takagi ,  Takashi Shigematsu ,  Takahide Kimura ,  Seiichi Imamizo

IPC分类号： B29C33/20 ,  B29C33/42 ,  B29C33/76 ,  B29C45/36 ,  B29C45/80 ,  B29D11/00 ,  B29L22/00 ,  B29L31/36 ,  G02B6/36 ,  G02B6/38

CPC分类号： B29D11/0075 ,  B29C33/202 ,  B29C45/36 ,  G02B6/381 ,  G02B6/3865 ,  G02B6/3885

摘要： A method of molding a ferrule of plastic resin provided with at least one hole having a small diameter and positioned at a predetermined position by a mold having a pair of associated molding ferrule halves, including the steps of arranging a molding core having at least one pin for defining the hole in a cavity defined by the pair of molding ferrule halves, holding the molding ferrule halves by a clamping force, the molding ferrule halves having inner members for positioning the pin and being free from the clamping force, supplying plastic resin into said cavity and pressing the inner members of the molding ferrule halves by a force separate from the mold clamping force.

公开(公告)号：US4517648A

公开(公告)日：1985-05-14

申请号：US399955

申请日：1982-07-19

申请人： Toshikazu Ina ,  Hisasi Kawai ,  Tokio Kohama ,  Hideki Obayashi ,  Daisaku Sawada ,  Takashi Shigematsu

发明人： Toshikazu Ina ,  Hisasi Kawai ,  Tokio Kohama ,  Hideki Obayashi ,  Daisaku Sawada ,  Takashi Shigematsu

IPC分类号： G01L23/08 ,  F02D45/00 ,  G01L5/00 ,  G01M15/04 ,  G01L23/32 ,  G01M15/00 ,  G01P15/11

CPC分类号： G01M15/042

摘要： A torque variation in an internal combustion engine due to the combustion variations is detected at each predetermined period. An average torque variation to be compared with the detected torque variation is predetermined experimentally based on the engine speed and the intake manifold pressure and is stored in a memory. The number of the detected torque variations which exceed the average torque variation multiplied by a predetermined constant is counted, and if the ratio of the counted number to the total number of the detected torque variations is larger than a predetermined reference value, then the presence of a torque variation is determined.

摘要翻译： 在每个预定周期检测由于燃烧变化引起的内燃机中的扭矩变化。 基于发动机转速和进气歧管压力，与实际检测到的扭矩变化相比较的平均扭矩变化是预先确定的，并存储在存储器中。 对超过平均转矩变化乘以预定常数的检测转矩变化的次数进行计数，如果计数值与检测到的转矩变化量的总数之比大于规定的基准值，则存在 确定扭矩变化。

公开(公告)号：US08748266B2

公开(公告)日：2014-06-10

申请号：US13291999

申请日：2011-11-08

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20100173461A1

公开(公告)日：2010-07-08

申请号：US12724323

申请日：2010-03-15

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。