公开(公告)号：US4563807A

公开(公告)日：1986-01-14

申请号：US596592

申请日：1984-04-04

申请人： Hiroyuki Sakai ,  Toyoki Takemoto ,  Kenji Kawakita ,  Tsutomu Fujita ,  Atsuko Akiyama

发明人： Hiroyuki Sakai ,  Toyoki Takemoto ,  Kenji Kawakita ,  Tsutomu Fujita ,  Atsuko Akiyama

IPC分类号： H01L21/20 ,  H01L21/203 ,  H01L21/285 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L21/225

CPC分类号： H01L29/7325 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02631 ,  H01L21/28525 ,  Y10S148/123 ,  Y10S148/124 ,  Y10S148/169

摘要： Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.

摘要翻译： 诸如双极晶体管的半导体器件通过分子束外延制造，其中发射极层（27）和多晶硅的覆盖接触区域（28）在硅衬底（23 + 26）上连续生长而不破坏高真空，因此 消除多晶硅层（28）下的自然氧化膜的不利界面和不利的供体 - 受体补偿，同时实现良好控制的hFE并实现浅发射极结。

公开(公告)号：US4563227A

公开(公告)日：1986-01-07

申请号：US660255

申请日：1984-10-12

申请人： Hiroyuki Sakai ,  Kenji Kawakita ,  Tsutomu Fujita ,  Toyoki Takemoto

发明人： Hiroyuki Sakai ,  Kenji Kawakita ,  Tsutomu Fujita ,  Toyoki Takemoto

IPC分类号： H01L21/762 ,  H01L21/38 ,  H01L21/467

CPC分类号： H01L21/76232 ,  H01L21/762

摘要： The invention provides a method for manufacturing a semiconductor device, wherein a semiconductor substrate is vertically etched to form a groove, antioxidant insulating films are formed on the side walls of the groove, and local oxidation is performed. Lateral extrusion of an oxide film which is a so-called bird's beak and a projection of the oxide film which is a so-called bird's head are substantially eliminated. As a result, the active region of the transistor, that is, the element formation region may not be narrowed, providing high packing density and high precision. Furthermore, the surface of the semiconductor substrate is flattened to prevent short-circuiting and disconnections of wiring layers. Stable manufacturing process provides a high yield of the semiconductor device. Electrical characteristics of the semiconductor device are greatly improved.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中半导体衬底被垂直蚀刻以形成沟槽，在沟槽的侧壁上形成抗氧化绝缘膜，并进行局部氧化。 基本上消除了所谓的鸟喙的氧化膜的侧向挤出和所谓的鸟头的氧化膜的突起。 结果，晶体管的有源区，即元件形成区域可能不会变窄，提供高的堆积密度和高精度。 此外，半导体衬底的表面被平坦化以防止布线层的短路和断开。 稳定的制造工艺提供了高产量的半导体器件。 半导体器件的电气特性大大提高。

公开(公告)号：US4814287A

公开(公告)日：1989-03-21

申请号：US82212

申请日：1987-08-06

申请人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

发明人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

IPC分类号： H01L27/00 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8236 ,  H01L27/06 ,  H01L27/088 ,  H01L21/76 ,  H01L21/95

CPC分类号： H01L21/743 ,  H01L21/76245 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/7627 ,  H01L21/76281

摘要： A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced. In addition, in such transistors which are completely separated, the parasitic effect with the circumference is completely prevented so that excellent characteristics can be provided.

摘要翻译： 一种制造双极型MOS型半导体集成电路器件的方法或者具有高集成度和高​​性能的两种类型的集成方法，其中电路包括第一器件区域，其中第一器件区域的侧表面和整个区域 有源区的下部由氧化硅制成，其第二器件区的有源区的侧表面和下部的一部分由氧化硅制成。 根据本发明，底部开放的晶体管和其底部未打开的晶体管可以自由地设置在基板上，从而将晶体管分成从基板提供电压的晶体管和晶体管 不能从基板供给电压，从而可以减少传统上需要的布线。 此外，在完全分离的这种晶体管中，完全防止与圆周的寄生效应，从而可以提供优异的特性。

公开(公告)号：US4615746A

公开(公告)日：1986-10-07

申请号：US652096

申请日：1984-09-19

申请人： Kenji Kawakita ,  Hiroyuki Sakai ,  Toyoki Takemoto

发明人： Kenji Kawakita ,  Hiroyuki Sakai ,  Toyoki Takemoto

IPC分类号： H01L21/22 ,  H01L21/762 ,  H01L21/225 ,  H01L21/302

CPC分类号： H01L21/22 ,  H01L21/76264 ,  H01L21/76281

摘要： A method of fabricating a semiconductor device comprises the steps of forming oxidation-resistive films on the surface and sides of a protrusion formed on a semiconductor substrate, forming grooves at the bottom of the sides of the protrusion, forming highly doped impurity diffusion regions in the groove surfaces, and subjecting the grooves to selective oxidation to form an oxide film under the bottom of the protrusion while a highly doped impurity diffusion region is formed, and forming a device in the protrusion.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在形成在半导体衬底上的突起的表面和侧面上形成耐氧化膜，在突起的侧面的底部形成凹槽，在其中形成高掺杂杂质扩散区 凹槽表面，并且使凹槽经受选择性氧化，以在突起的底部形成氧化膜，同时形成高度掺杂的杂质扩散区，并在突起中形成器件。

公开(公告)号：US4484211A

公开(公告)日：1984-11-20

申请号：US542555

申请日：1983-10-17

申请人： Toyoki Takemoto ,  Tsutomu Fujita ,  Hiroyuki Sakai ,  Haruyasu Yamada

发明人： Toyoki Takemoto ,  Tsutomu Fujita ,  Hiroyuki Sakai ,  Haruyasu Yamada

IPC分类号： H01L29/06 ,  H01L29/732 ,  H01L27/04 ,  H01L29/04 ,  H01L29/72

CPC分类号： H01L29/7325 ,  H01L29/0649

摘要： A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.

摘要翻译： 一种半导体集成电路器件，其中氧化物隔离双极晶体管的发射极的侧表面被绝缘化合物或区域包围，使得发射极和基极之间的电容降低，并且通过自对准形成基极， 活性碱在外部碱基和发光体之间的影响可以忽略不计。 因此，基极电阻和寄生电容降低。

公开(公告)号：US4459496A

公开(公告)日：1984-07-10

申请号：US251966

申请日：1981-04-03

申请人： Haruyasu Yamada ,  Toyoki Takemoto ,  Tadao Komeda ,  Tsutomu Fujita ,  Yuichi Hirofuji ,  Hiroyuki Sakai

发明人： Haruyasu Yamada ,  Toyoki Takemoto ,  Tadao Komeda ,  Tsutomu Fujita ,  Yuichi Hirofuji ,  Hiroyuki Sakai

IPC分类号： H03K19/091 ,  H03K19/092

CPC分类号： H03K19/091

摘要： In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

摘要翻译： 在堆叠的多层IIL（集成注入逻辑）电路中，功率消耗可以显着降低，由用于移位电平的晶体管之一提供由IIL恒流电路或电阻构成的放电电路 从顶层的IIL电路到底层的IIL电路的信号，从而防止它们之间的信号传输劣化。 充电电路可以被添加到另一个晶体管，而二极管可以插在这些晶体管之间。 可以在相邻层之间插入附加的二极管，以加速从一个层到另一个上层的信号传输。

公开(公告)号：US08718359B2

公开(公告)日：2014-05-06

申请号：US12728570

申请日：2010-03-22

申请人： Hiroyuki Sakai ,  Kiyoshi Umeda

发明人： Hiroyuki Sakai ,  Kiyoshi Umeda

IPC分类号： G06K9/00 ,  G06K9/40

CPC分类号： G06T5/001 ,  G06K9/00664 ,  G06T11/001 ,  G06T2207/30168 ,  H04N1/56 ,  H04N1/60 ,  H04N1/6072

摘要： An image processing apparatus and a method thereof for correcting image data in accordance with a feature of the image data, calculates a brightness component of image data and a color difference component of image data, determines whether the image data is a nightscape image or an underexposed image using the calculated brightness component and color difference component, and corrects the image data which has been determined as a nightscape image or an underexposed image.

摘要翻译： 一种用于根据图像数据的特征校正图像数据的图像处理装置及其方法，计算图像数据的亮度分量和图像数据的色差分量，确定图像数据是夜景图像还是曝光不足 使用所计算的亮度分量和色差分量的图像，并校正已被确定为夜景图像或曝光不足的图像的图像数据。

公开(公告)号：US08575731B2

公开(公告)日：2013-11-05

申请号：US12999472

申请日：2009-06-15

申请人： Shinji Ujita ,  Takeshi Fukuda ,  Hiroyuki Sakai

发明人： Shinji Ujita ,  Takeshi Fukuda ,  Hiroyuki Sakai

IPC分类号： H01L23/58

CPC分类号： H01P5/10 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/19104 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor integrated circuit device with a balun which is formed above a conductive semiconductor substrate and which includes a dielectric film, an unbalanced line for transmitting an unbalanced signal, and balanced lines for transmitting a balanced signal. The unbalanced line is placed opposite to the balanced lines via a nano-composite film that is a region of the dielectric film. The nano-composite film, interposed between the unbalanced line and the balanced lines, has a relative permittivity higher than that of other regions of the dielectric film. This allows suppression of electromagnetic coupling of transmission lines or passive elements other than the balun, thereby providing a semiconductor device with a wide-band and small-size balun.

摘要翻译： 一种具有平衡 - 不平衡转换器的半导体集成电路器件，其形成在导电半导体衬底之上，并且包括电介质膜，用于传输不平衡信号的不平衡线以及用于传输平衡信号的平衡线。 不平衡线通过作为电介质膜的区域的纳米复合膜与平衡线相对放置。 夹在不平衡线和平衡线之间的纳米复合膜的介电常数比电介质膜的其它区域的介电常数高。 这允许抑制除了平衡 - 不平衡变换器之外的传输线或无源元件的电磁耦合，从而提供具有宽带和小尺寸平衡 - 不平衡转换器的半导体器件。

公开(公告)号：US20130081919A1

公开(公告)日：2013-04-04

申请号：US13702906

申请日：2011-06-10

申请人： Hiroyuki Sakai ,  Kazutoshi Yoshida ,  Norihiro Maezato

发明人： Hiroyuki Sakai ,  Kazutoshi Yoshida ,  Norihiro Maezato

IPC分类号： F16D11/10

CPC分类号： F16D11/10 ,  F16D1/108 ,  F16D11/14 ,  G01M15/02

摘要： A shaft connection structure connects a pair of rotating shafts by a fit between a pair of spline shafts, wherein the pair of rotating shafts are provided with corresponding ones of the pair of spline shafts. The shaft connection structure includes a shaft connection assist device. The shaft connection assist device includes a centering ring and centering pins. The centering ring is arranged outside of a first one of the spline shafts and coaxially with the first spline shaft. The centering pins are provided outside of a second one of the spline shafts. The centering pins engage with an outer peripheral surface of the centering ring and bring a shaft axis of the first spline shaft and a shaft axis of the second spline shaft into a range enabling the fit therebetween.

摘要翻译： 轴连接结构通过一对花键轴之间的配合连接一对旋转轴，其中一对旋转轴设置有一对花键轴中的对应的一对花键轴。 轴连接结构包括轴连接辅助装置。 轴连接辅助装置包括定心环和定心销。 定心环布置在第一个花键轴的外侧，与第一花键轴同轴。 定心销设置在第二个花键轴的外侧。 定心销与定心环的外周面接合，使第一花键轴的轴线和第二花键轴的轴线成为能够在其间进行配合的范围。

公开(公告)号：US08018372B2

公开(公告)日：2011-09-13

申请号：US12678586

申请日：2008-07-28

申请人： Noboru Negoro ,  Takeshi Fukuda ,  Hiroyuki Sakai

发明人： Noboru Negoro ,  Takeshi Fukuda ,  Hiroyuki Sakai

IPC分类号： G01S13/58

CPC分类号： G01S13/325 ,  G01S13/931 ,  G01S2013/9375 ,  G01S2013/9378

摘要： The spread spectrum radar apparatus in the present invention (i) includes: a transmission code generator (110); a reception code generator (121) generating a reception code obtained by delaying a transmission code; a spread modulator (112) spread-modulating a signal generated by a local oscillator (111) using the transmission code; a transmission antenna (113) transmitting the spread-modulated signal; a reception antenna (120) receiving a signal; a spread demodulator (122) demodulating the signal using the reception code to provide a correlation signal; a mixer (123) mixing the correlation signal and the signal generated by the local oscillator (111) to generate a radar signal; a virtual image determining unit (130) determining a virtual image; and a radar signal calculation device (160) calculating the radar signal using a virtual image determination signal, and (ii) adds a calculation and an offset signal for suppressing a peak intensity of the virtual image when the virtual image occurs.

摘要翻译： 本发明（i）中的扩频雷达装置包括：发送码发生器（110）; 产生通过延迟传输码而获得的接收码的接收码发生器（121）; 扩展调制器（112）使用所述传输码扩展调制由本地振荡器（111）产生的信号; 发送所述扩展调制信号的发送天线（113） 接收天线（120），接收信号; 扩展解调器（122），使用接收码解调信号以提供相关信号; 混合器（123），混合相关信号和由本地振荡器（111）产生的信号，以产生雷达信号; 虚拟图像确定单元（130），确定虚拟图像; 以及雷达信号计算装置（160），使用虚拟图像确定信号计算雷达信号，并且（ii）在虚拟图像发生时添加用于抑制虚拟图像的峰值强度的计算和偏移信号。