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    Method for manufacturing a semiconductor device
    2.
    发明授权
    Method for manufacturing a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US4563227A

    公开(公告)日：1986-01-07

    申请号：US660255

    申请日：1984-10-12

    申请人： Hiroyuki Sakai ,  Kenji Kawakita ,  Tsutomu Fujita ,  Toyoki Takemoto

    发明人： Hiroyuki Sakai ,  Kenji Kawakita ,  Tsutomu Fujita ,  Toyoki Takemoto

    IPC分类号： H01L21/762 ,  H01L21/38 ,  H01L21/467

    CPC分类号： H01L21/76232 ,  H01L21/762

    摘要： The invention provides a method for manufacturing a semiconductor device, wherein a semiconductor substrate is vertically etched to form a groove, antioxidant insulating films are formed on the side walls of the groove, and local oxidation is performed. Lateral extrusion of an oxide film which is a so-called bird's beak and a projection of the oxide film which is a so-called bird's head are substantially eliminated. As a result, the active region of the transistor, that is, the element formation region may not be narrowed, providing high packing density and high precision. Furthermore, the surface of the semiconductor substrate is flattened to prevent short-circuiting and disconnections of wiring layers. Stable manufacturing process provides a high yield of the semiconductor device. Electrical characteristics of the semiconductor device are greatly improved.

    摘要翻译： 本发明提供一种制造半导体器件的方法，其中半导体衬底被垂直蚀刻以形成沟槽，在沟槽的侧壁上形成抗氧化绝缘膜，并进行局部氧化。 基本上消除了所谓的鸟喙的氧化膜的侧向挤出和所谓的鸟头的氧化膜的突起。 结果，晶体管的有源区，即元件形成区域可能不会变窄，提供高的堆积密度和高精度。 此外，半导体衬底的表面被平坦化以防止布线层的短路和断开。 稳定的制造工艺提供了高产量的半导体器件。 半导体器件的电气特性大大提高。

    Method of manufacturing a semiconductor integrated circuit device
    3.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US4814287A

    公开(公告)日：1989-03-21

    申请号：US82212

    申请日：1987-08-06

    申请人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

    发明人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

    IPC分类号： H01L27/00 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8236 ,  H01L27/06 ,  H01L27/088 ,  H01L21/76 ,  H01L21/95

    CPC分类号： H01L21/743 ,  H01L21/76245 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/7627 ,  H01L21/76281

    摘要： A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced. In addition, in such transistors which are completely separated, the parasitic effect with the circumference is completely prevented so that excellent characteristics can be provided.

    摘要翻译： 一种制造双极型MOS型半导体集成电路器件的方法或者具有高集成度和高​​性能的两种类型的集成方法，其中电路包括第一器件区域，其中第一器件区域的侧表面和整个区域 有源区的下部由氧化硅制成，其第二器件区的有源区的侧表面和下部的一部分由氧化硅制成。 根据本发明，底部开放的晶体管和其底部未打开的晶体管可以自由地设置在基板上，从而将晶体管分成从基板提供电压的晶体管和晶体管 不能从基板供给电压，从而可以减少传统上需要的布线。 此外，在完全分离的这种晶体管中，完全防止与圆周的寄生效应，从而可以提供优异的特性。

    Method of manufacturing isolated semiconductor devices
    5.
    发明授权
    Method of manufacturing isolated semiconductor devices 失效
    制造隔离半导体器件的方法

    公开(公告)号：US4685198A

    公开(公告)日：1987-08-11

    申请号：US758962

    申请日：1985-07-25

    申请人： Kenji Kawakita ,  Noboru Nomura ,  Toyoki Takemoto

    发明人： Kenji Kawakita ,  Noboru Nomura ,  Toyoki Takemoto

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/06

    CPC分类号： H01L21/76264 ,  H01L21/762 ,  H01L21/763 ,  H01L21/76281 ,  H01L21/76283 ,  Y10S148/05 ,  Y10S148/115 ,  Y10S438/973

    摘要： Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.

    摘要翻译： 公开了通过采用选择氧化技术（LOCOS技术）将晶体管完全隔离的方法。 更具体地，在{100}硅衬底的表面中形成垂直开口，并且由该表面和这些开口的一部分侧壁形成抗氧化膜。 相继地，通过用具有取向各向异性的蚀刻剂进行蚀刻，在开口的侧壁中以高精度形成凹痕。 通过使用抗氧化膜作为掩模进行氧化，从开口侧壁中的凹陷生长的氧化膜与从相邻凹坑生长的另一氧化膜连接。 因此，在与衬底电隔离的硅的有源区中形成的晶体管的寄生电容小，并且可以形成为小尺寸，使得其具有适合于VLSI的特征，即高速度，低功耗， 和可加工性的高密度集成。

    ATM switching network and ATM switching system in which the transfer of inputted cells is controlled by control cells, and signal processing method in ATM switching network
    6.
    发明授权
    ATM switching network and ATM switching system in which the transfer of inputted cells is controlled by control cells, and signal processing method in ATM switching network 有权
    ATM交换网络和ATM交换系统，其中输入的小区的传输由控制小区控制，以及ATM交换网络中的信号处理方法

    公开(公告)号：US06396808B1

    公开(公告)日：2002-05-28

    申请号：US09519417

    申请日：2000-03-06

    申请人： Masao Kunimoto ,  Kenji Kawakita ,  Shinichi Iwaki ,  Satoshi Shimizu

    发明人： Masao Kunimoto ,  Kenji Kawakita ,  Shinichi Iwaki ,  Satoshi Shimizu

    IPC分类号： H04L1256

    CPC分类号： H04L49/309 ,  H04L2012/5627 ,  H04L2012/563 ,  H04Q11/0478

    摘要： A signal processing method for an ATM switching network formed by connecting a plurality of ATM switching networks in which header conversion tables of line interfaces can be rewritten by control cells, includes in response to occurrence of an abnormality in a call control processor of a ATM switching system A, informing an ATM switching system B of the occurrence of the abnormality, transferring call control information in the ATM switching system A to the ATM switching system B, rewriting header conversion tables included in a plurality of line interfaces of the ATM switching system A by using control cells generated by the ATM switching system A and thereby transferring signal channel cells arriving at the ATM switching system A after occurrence of the abnormality to the ATM switching system B, and rewriting header conversion tables included in a plurality of line interfaces of the ATM switching system A by using control cells generated by the ATM switching system B and thereby making a call control processor of the ATM switching system B effect route control of information channel cells within the ATM switching system A.

    摘要翻译： 一种用于通过连接多个ATM交换网络形成的ATM交换网络的信号处理方法，其中线路接口的报头转换表可由控制小区重写，包括响应于ATM交换机的呼叫控制处理器中发生异常 系统A通知ATM交换系统B发生异常，将ATM交换系统A中的呼叫控制信息传送到ATM交换系统B，重写包括在ATM交换系统A的多个线路接口中的报头转换表 通过使用由ATM交换系统A生成的控制信元，从而在ATM交换系统B发生异常之后传送到达ATM交换系统A的信道信元，并重写包含在ATM交换系统A的多个线路接口中的报头转换表 ATM交换系统A通过使用由ATM交换系统B生成的控制信元，从而进行maki ATM交换系统B的呼叫控制处理器对ATM交换系统A内的信道信元进行路由控制。

    Fine pattern forming method
    8.
    发明授权
    Fine pattern forming method 失效
    精细图案形成方法

    公开(公告)号：US5169494A

    公开(公告)日：1992-12-08

    申请号：US742550

    申请日：1991-08-08

    申请人： Kazuhiko Hashimoto ,  Taichi Koizumi ,  Kenji Kawakita ,  Noboru Nomura

    发明人： Kazuhiko Hashimoto ,  Taichi Koizumi ,  Kenji Kawakita ,  Noboru Nomura

    IPC分类号： G03F7/039 ,  G03F7/09

    CPC分类号： G03F7/094 ,  G03F7/039

    摘要： The present invention provides a method of forming a fine pattern comprising the steps of forming on a semiconductor substrate an organic polymer film and heat treating it, forming on the organic polymer film an inorganic film and heat treating it, forming on the inorganic film an electron beam resist film and heat treating it, drawing a pattern on the resist film, developing it to form a resist pattern, and etching the inorganic film and the organic polymer film using the resist pattern as a mask, wherein the improvement comprises using one substance selected from the group consisting of a polyphenylene sulfide, a derivative thereof, and a polymer represented by the formula (I): ##STR1## where n is a positive integer, for forming at least one of the organic polymer film and the electron beam resist film. According to the present invention, it is possible to prevent charging by incident electrons, thereby keeping free of field butting and reduction of overlay accuracy, and to form an accurate and vertical fine resist pattern.

    摘要翻译： 本发明提供一种形成精细图案的方法，包括以下步骤：在半导体衬底上形成有机聚合物膜并进行热处理，在有机聚合物膜上形成无机膜并进行热处理，在无机膜上形成电子 抗蚀剂膜并对其进行热处理，在抗蚀剂膜上绘制图案，将其显影以形成抗蚀剂图案，并使用抗蚀剂图案作为掩模蚀刻无机膜和有机聚合物膜，其中改进包括使用选择的一种物质 由聚苯硫醚，其衍生物和由式（I）表示的聚合物组成：其中n为正整数，用于形成至少一个有机聚合物膜和电子 光束抗蚀膜。 根据本发明，可以防止入射电子的充电，从而保持无间隙对接和降低覆盖精度，并形成精确和垂直的精细抗蚀剂图案。

    Method and system for data transmission
    9.
    发明授权
    Method and system for data transmission 失效
    数据传输方法和系统

    公开(公告)号：US4855995A

    公开(公告)日：1989-08-08

    申请号：US7339

    申请日：1987-01-27

    申请人： Kunio Hiyama ,  Kenji Kawakita ,  Osamu Takada

    发明人： Kunio Hiyama ,  Kenji Kawakita ,  Osamu Takada

    IPC分类号： H04L12/43 ,  H04M9/02

    CPC分类号： H04M9/022 ,  H04L12/43

    摘要： Herein disclosed is a data communication system in which a plurality of node equipments are linked to a common signal transmission line so that the data may be communicated between the respective node equipments. The data communication system is characterized: in that at least one of the node equipments includes means for generating and transmitting repeatedly for a predetermined period the channel which contains a data transmission bit and a validity bit for the former bit; and in that each of the node equipments linked to the common signal transmission line partly sends out the data through said channel and partly makes the validity indicating bit indicate an invalid state, when the speed of said data is so slower than the predetermined period of said channel that the data to be sent out for the predetermined period are out of time thereby to make it possible to effect the data transmission at an arbitrary speed shorter than said predetermined period.Herein also disclosed is a data communication system in which a plurality of node equipments are jointed by a common transmission loop line and in which the information of multiple channels is repeatedly transmitted for a predetermined period to said transmission loop line so that the channel information may be sent and received between terminal equipments linked to said node equipments. The data communication system is characterized in that an identical pattern for synchronization is inserted into and transmitted by the plural head channels of each period so that the synchronization is effected at each of said node equipments by detecting the synchronizing pattern received by means of a detecting circuit.

    摘要翻译： 这里公开了一种数据通信系统，其中多个节点设备链接到公共信号传输线，使得可以在各个节点设备之间传送数据。 数据通信系统的特征在于：节点设备中的至少一个包括用于在预定周期内重复生成和发送包含前一比特的数据传输比特和有效比特的信道的装置; 并且，连接到公共信号传输线路的每个节点设备部分地通过所述信道发送数据，并且部分地使有效指示位指示无效状态，当所述数据的速度比所述数据的预定时间慢的时候 在预定时间段内要发送的数据的时间是超时的，从而使得可以以比所述预定周期短的任意速度实现数据传输。 这里还公开了一种数据通信系统，其中多个节点设备由公共传输环路线连接，并且其中将多个信道的信息重复发送一段预定时间段到所述传输环路线，使得信道信息可以是 在与所述节点设备连接的终端设备之间发送和接收。 数据通信系统的特征在于，用于同步的相同模式被插入每个周期的多个头信道并由其发送，从而通过检测通过检测电路接收的同步模式来在每个所述节点设备处实现同步 。