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    Semiconductor memory including reduced capacitive coupling between adjacent bit lines
    1.
    发明授权
    Semiconductor memory including reduced capacitive coupling between adjacent bit lines 失效
    半导体存储器包括相邻位线之间的电容耦合减小

    公开(公告)号：US5099452A

    公开(公告)日：1992-03-24

    申请号：US371904

    申请日：1989-06-27

    申请人： Hiroyuki Yamakoshi ,  Hidehiro Asai

    发明人： Hiroyuki Yamakoshi ,  Hidehiro Asai

    IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C7/18 ,  G11C8/16 ,  G11C11/401

    CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C8/16

    摘要： A semiconductor memory apparatus comprises a plurality of complementary bit line pairs for accessing memory cells. Each of the memory cells is accessed by two complementary bit line pairs. Each of the complementary bit line pairs is connected to a corresponding sense amp circuit for amplifying a signal level difference between bit lines of a corresponding bit line pair. A plurality of sealed lines, each being connected to ground and being positioned between two adjacent bit lines of different complementary bit line pairs, are provided to avoid the formation of a line-to-line capacitance between the two adjacent bit lines.

    摘要翻译： 半导体存储器装置包括用于访问存储器单元的多个互补位线对。 每个存储器单元由两个互补位线对访问。 每个互补位线对连接到对应的读出放大器电路，用于放大相应位线对的位线之间的信号电平差。 提供了多个密封线，每条被连接到地并且位于不同互补位线对的两个相邻位线之间，以避免在两个相邻位线之间形成线间电容。

    Semiconductor memory that enables high speed operation
    2.
    发明授权
    Semiconductor memory that enables high speed operation 失效
    可实现高速运行的半导体存储器

    公开(公告)号：US06392956B2

    公开(公告)日：2002-05-21

    申请号：US09863322

    申请日：2001-05-24

    申请人： Yoshinori Matsui ,  Hiroyuki Yamakoshi

    发明人： Yoshinori Matsui ,  Hiroyuki Yamakoshi

    IPC分类号： G11C800

    CPC分类号： G11C29/70 ,  G11C8/12

    摘要： A semiconductor memory includes a block selection circuit, a redundancy main word decoder, a word reset circuit, and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.

    摘要翻译： 半导体存储器包括块选择电路，冗余主字解码器，字复位电路和字驱动器电路。 块选择电路基于地址信号输出块选择信号。 冗余主字解码器响应于块选择信号产生冗余主字信号。 字复位电路响应于冗余主字信号输出字复位信号。 字驱动器电路响应于字复位信号驱动字线之一，指示字驱动器电路的选择的主字信号和指示字线之一的选择的字解码信号。

    Semiconductor memory device having push-pull type output circuit formed by two N-channel MOS transistors
    3.
    发明授权
    Semiconductor memory device having push-pull type output circuit formed by two N-channel MOS transistors 有权
    具有由两个N沟道MOS晶体管形成的推挽型输出电路的半导体存储器件

    公开(公告)号：US6166965A

    公开(公告)日：2000-12-26

    申请号：US431334

    申请日：1999-10-28

    申请人： Hiroyuki Yamakoshi

    发明人： Hiroyuki Yamakoshi

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04

    CPC分类号： G11C7/1048 ,  G11C7/1051 ,  G11C7/1072

    摘要： In a semiconductor memory device including a data bus, a data bus charging circuit for charging the data bus, a data bus discharging circuit for discharging the data bus in accordance with a cell read data signal, and a push-pull type output circuit formed by a first N-channel MOS transistor connected between a first power supply terminal and an output terminal and a second N-channel MOS transistor connected between the output terminal and a second power supply terminal, a step-up circuit is connected between the data bus and a gate of the first N-channel MOS transistor to generate a step-up voltage in accordance with a voltage at the data bus.

    摘要翻译： 在包括数据总线的半导体存储器件，用于对数据总线充电的数据总线充电电路，用于根据单元读取数据信号对数据总线进行放电的数据总线放电电路以及由 - 连接在第一电源端子和输出端子之间的第一N沟道MOS晶体管和连接在输出端子和第二电源端子之间的第二N沟道MOS晶体管，升压电路连接在数据总线和 第一N沟道MOS晶体管的栅极，以根据数据总线上的电压产生升压电压。

    Semiconductor memory device and method for replacing redundancy circuit
    6.
    发明授权
    Semiconductor memory device and method for replacing redundancy circuit 有权
    用于替换冗余电路的半导体存储器件和方法

    公开(公告)号：US06618300B2

    公开(公告)日：2003-09-09

    申请号：US09965199

    申请日：2001-09-27

    申请人： Hiroyuki Yamakoshi

    发明人： Hiroyuki Yamakoshi

    IPC分类号： G11C700

    CPC分类号： G11C29/80

    摘要： In a semiconductor memory device, a plurality of banks is arranged on a semiconductor substrate. A plurality of memory array groups is arranged on the plates. Redundant memory cell array groups replace a memory cell array, including a defective memory cell, and are arranged at every plate. Subword selection circuits switch subword selection lines at every plate. Each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundant subword selection line of the redundant memory cell array arranged on the other adjacent plate.

    摘要翻译： 在半导体存储器件中，在半导体衬底上布置有多个堤。 多个存储器阵列组布置在板上。 冗余存储单元阵列组替换存储单元阵列，包括有缺陷的存储单元，并且布置在每个板上。 子字选择电路在每个板上切换子字选择线。 子字选择电路中的每一个具有选择单元，其选择属于其的板上的子字选择线和布置在另一相邻板上的冗余存储单元阵列的冗余子选择线。