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    Light diffusion plate and its production process
    1.
    发明授权
    Light diffusion plate and its production process 失效
    光扩散板及其生产工艺

    公开(公告)号：US07727626B2

    公开(公告)日：2010-06-01

    申请号：US11949801

    申请日：2007-12-04

    申请人： Hisao Inokuma ,  Toshihiko Higuchi ,  Akira Mitsui

    发明人： Hisao Inokuma ,  Toshihiko Higuchi ,  Akira Mitsui

    IPC分类号： B32B5/16 ,  B05D5/06 ,  G03B21/56 ,  G03B21/60

    CPC分类号： G03B21/62 ,  C03C17/3405 ,  G02B5/0242 ,  G02B5/0268 ,  G02B5/0278 ,  Y10T428/249921 ,  Y10T428/25

    摘要： A light diffusion plate has a substrate and a light diffusion layer formed on the substrate. The light diffusion layer is composed of at least two layers: a first light diffusion layer containing a first matrix and a first light diffusion agent having a refractive index difference Δn1 of 0.04≦Δn1≦0.2 with the first matrix, and a second light diffusion layer containing a second matrix and a second light diffusion agent having a refractive index difference Δn2 of 0.005≦Δn2≦0.01 with the second matrix. The volume fraction of the first light diffusion agent in the first light diffusion layer is less than 40%, the volume fraction of the second light diffusion agent in the second light diffusion layer is at least 40% and the total thickness of the light diffusion layers is from 5 to 200 μm after curing.

    摘要翻译： 光扩散板具有形成在基板上的基板和光扩散层。 光扩散层由至少两层构成：包含第一基质的第一光扩散层和折射率差为Dgr的第一光扩散剂，n1为0.04＆nlE;＆Dgr; n1＆nlE; 0.2与第一基质，以及 第二光扩散层，其含有第二基体和第二光扩散剂，所述第二光扩散剂的折射率差为＆Dgr; n2为0.005＆nlE;＆Dgr; n2＆nlE; 0.01与第二矩阵。 第一光扩散层中的第一光扩散剂的体积分率小于40％，第二光扩散层中第二光扩散剂的体积分数为40％以上，光扩散层的总厚度 固化后为5〜200μm。

    LIGHT DIFFUSION PLATE AND ITS PRODUCTION PROCESS
    2.
    发明申请
    LIGHT DIFFUSION PLATE AND ITS PRODUCTION PROCESS 失效
    光扩散板及其生产工艺

    公开(公告)号：US20080090063A1

    公开(公告)日：2008-04-17

    申请号：US11949801

    申请日：2007-12-04

    申请人： Hisao INOKUMA ,  Toshihiko Higuchi ,  Akira Mitsui

    发明人： Hisao INOKUMA ,  Toshihiko Higuchi ,  Akira Mitsui

    IPC分类号： B32B3/00 ,  B05D5/06

    CPC分类号： G03B21/62 ,  C03C17/3405 ,  G02B5/0242 ,  G02B5/0268 ,  G02B5/0278 ,  Y10T428/249921 ,  Y10T428/25

    摘要： To provide a transmission screen to be used for a PTV, particularly a high rigidity transmission screen suitably used for a high precision PTV on which an optical engine such as MD is mounted, capable of coping with enlargement of the screen, and a diffusion plate to be used therefor. A light diffusion plate comprising a substrate and a light diffusion layer formed on the substrate, wherein the light diffusion layer comprises at least two layers of a first light diffusion layer containing a first matrix and a first light diffusion agent having a refractive index difference Δn1 of 0.04≦Δn1≦0.2 with the first matrix, and a second light diffusion layer containing a second matrix and a second light diffusion agent having a refractive index difference Δn2 of 0.005≦Δn2≦0.04 with the second matrix; the volume fraction of the first light diffusion agent in the first light diffusion layer is less than 40%, and the volume fraction of the second light diffusion agent in the second light diffusion layer is at least 40%; and the total thickness of the light diffusion layers is from 5 to 200 μm by the thickness after curing.

    摘要翻译： 为了提供用于PTV的传输屏幕，特别是适用于其上安装有诸如MD的光学引擎的高精度PTV的高刚性传输屏幕，能够应对屏幕的扩大，以及扩散板 用于此。 1.一种光扩散板，包括基板和形成在所述基板上的光扩散层，其中，所述光扩散层包括至少两层含有第一基体的第一光扩散层和折射率差为Deltan的第一光扩散剂， 第一矩阵的第二光扩散层和折射率差为Deltan的第二光扩散剂的第二光扩散层为0.04 <= N / N 具有第二基体的0.005 <=ΔN2 <= 0.04的第二个<！ - SIPO

    Manufacturing method of semiconductor device
    4.
    发明申请
    Manufacturing method of semiconductor device 审中-公开
    半导体器件的制造方法

    公开(公告)号：US20120064669A1

    公开(公告)日：2012-03-15

    申请号：US13137813

    申请日：2011-09-14

    申请人： Toshihiko Higuchi

    发明人： Toshihiko Higuchi

    IPC分类号： H01L21/50

    CPC分类号： H01L21/6835 ,  H01L21/78

    摘要： The present invention relates to a method for manufacturing a semiconductor device, containing: a first step of producing a first component part of a semiconductor device on a first surface of a semiconductor wafer; a second step of laminating a support plate to the first surface of the semiconductor wafer, on which the first component part has been produced, through only a silicone resin layer therebetween; a third step of grinding a second surface opposing the first surface of the semiconductor wafer, in the state of the support plate being laminated, and then producing a second component part of the semiconductor device on the ground surface; and a fourth step of peeling off the silicone resin layer from the semiconductor wafer on which the first component part and the second component part have been produced, thereby removing the silicone resin layer and the support plate, and cutting the semiconductor wafer into a chip.

    摘要翻译： 半导体器件的制造方法技术领域本发明涉及一种半导体器件的制造方法，包括：在半导体晶片的第一面上制造半导体器件的第一部分的第一工序; 第二步骤，通过其间的硅树脂层将支撑板层压到已经制造了第一部件的半导体晶片的第一表面上; 在所述支撑板的层叠状态下研磨与所述半导体晶片的所述第一面相对的第二面的第三工序，然后在所述地面上制造所述半导体器件的第二部分; 以及从其上制造了第一部件和第二部件的半导体晶片剥离硅树脂层的第四步骤，从而除去硅树脂层和支撑板，并将半导体晶片切割成芯片。

    Semiconductor device and method for manufacturing the same
    5.
    发明申请
    Semiconductor device and method for manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20050023636A1

    公开(公告)日：2005-02-03

    申请号：US10928968

    申请日：2004-08-27

    申请人： Toshihiko Higuchi

    发明人： Toshihiko Higuchi

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

    CPC分类号： H01L21/76897 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66621

    摘要： The invention provides an improved semiconductor and an improved method for manufacturing the device. In a preferred embodiment, a gate electrode is formed on a semiconductor substrate through a gate dielectric layer. First and second impurity diffusion layers are formed in the semiconductor substrate on either side of the gate electrode, with the gate electrode interposed between the first and second impurity diffusion layers. Sidewall dielectric layers are formed on side surfaces of the gate electrode and configured so that the gate electrode has a width that increases gradually from a bottom of the gate electrode toward a top surface of the gate electrode. The first and second impurity diffusion layers are formed thick enough that the surfaces of the first and second impurity diffusion layers are higher than the interface between the semiconductor substrate and the gate dielectric layer. This allows a further miniaturized transistor with favorable transistor characteristics because the film thicknesses of the first and second impurity diffusion layers are maintained.

    摘要翻译： 本发明提供一种改进的半导体和改进的该器件制造方法。 在优选实施例中，栅电极通过栅介质层形成在半导体衬底上。 第一和第二杂质扩散层形成在栅电极的任一侧上的半导体衬底中，栅电极介于第一和第二杂质扩散层之间。 侧壁电介质层形成在栅电极的侧表面上并且被构造成使得栅电极具有从栅电极的底部朝向栅电极的顶表面逐渐增加的宽度。 第一和第二杂质扩散层形成得足够厚，使得第一和第二杂质扩散层的表面高于半导体衬底和栅极电介质层之间的界面。 这允许由于第一和第二杂质扩散层的膜厚被保持而具有良好晶体管特性的另一小型化晶体管。

    Semiconductor devices of the planar type bipolar transistors and combination bipolar/MIS type transistors
    6.
    发明授权
    Semiconductor devices of the planar type bipolar transistors and combination bipolar/MIS type transistors 失效
    平面型双极晶体管和组合双极/ MIS型晶体管的半导体器件

    公开(公告)号：US5404043A

    公开(公告)日：1995-04-04

    申请号：US139608

    申请日：1993-10-20

    申请人： Toshihiko Higuchi

    发明人： Toshihiko Higuchi

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L27/07 ,  H01L27/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/73 ,  H01L27/06 ,  H01L29/40

    CPC分类号： H01L29/7816 ,  H01L27/0722 ,  H01L29/42376 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66674 ,  H01L29/7801

    摘要： A sidewall construction is utilized in the fabrication of semiconductor devices comprising planar type bipolar transistors wherein the width of the sidewall construction can be accuracy controlled which, in turn, controls accuracy the channel length of the base of the planar type bipolar transistors. This technique provides ways of preventing short circuiting between the formed transistor collector and emitter regions of the planar type bipolar transistors. The sidewall construction can also be employed in fabrication combination planar type bipolar/MIS type transistors resulting in higher density of these structures over the prior art laterally positioned structures.

    摘要翻译： 侧壁结构用于制造包括平面型双极晶体管的半导体器件，其中侧壁结构的宽度可被精确控制，这进而控制平面型双极晶体管的基极的沟道长度的精度。 该技术提供了防止形成的晶体管集电极与平面型双极晶体管的发射极区之间的短路的方法。 侧壁结构也可以用在制造组合平面型双极/ MIS型晶体管中，导致这些结构比现有技术的横向定位结构更高的密度。

    Semiconductor device comprising MIS field-effect transistor, and method of fabricating the same
    9.
    发明授权
    Semiconductor device comprising MIS field-effect transistor, and method of fabricating the same 失效
    包含MIS场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US06740559B2

    公开(公告)日：2004-05-25

    申请号：US09984935

    申请日：2001-10-31

    申请人： Toshihiko Higuchi

    发明人： Toshihiko Higuchi

    IPC分类号： H01L218234

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656

    摘要： An objective of the present invention is to provide a method of fabricating a semiconductor device comprising a MIS field-effect transistor that makes it possible to prevent damage to edge portions of a gate oxide layer during ion implantation and also prevents the thickness of edge portions of a titanium silicide layer from becoming too great. Before n−-type regions 16 are formed, a silicon nitride layer 24 is formed to extend from corner portions 42 of a gate electrode 26 and over side surfaces of a gate oxide layer 20. Ion implantation is used to form the n−-type regions 16. The silicon nitride layer 24 has been positioned so as to shield the side surfaces of the gate oxide layer 20. This ensures that ions do not strike the side surfaces of the gate oxide layer 20 during the implantation. When a titanium silicide layer 28 is formed on the upper surface of the gate electrode 26, the silicide reaction of the silicon nitride layer 24 on the side surfaces of the gate electrode 26 is prevented.

    摘要翻译： 本发明的目的是提供一种制造半导体器件的方法，该半导体器件包括MIS场效应晶体管，其可以防止在离子注入期间对栅极氧化物层的边缘部分的损坏，并且还可以防止边缘部分的厚度 硅化钛层变得太大。在形成n +型区域16之前，形成氮化硅层24，以从栅电极26的拐角部分42和栅极氧化物层20的侧表面延伸。 使用离子注入来形成n +型区域16.氮化硅层24已经被定位成屏蔽了栅极氧化物层20的侧表面。这确保了离子不会撞击到 栅极氧化物层20。 当在栅电极26的上表面上形成硅化钛层28时，防止栅电极26的侧表面上的氮化硅层24的硅化物反应。

    Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors
    10.
    发明授权
    Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors 失效
    制造平面型极性晶体管和组合双极/ MIS型晶体管的方法

    公开(公告)号：US5281544A

    公开(公告)日：1994-01-25

    申请号：US818717

    申请日：1992-01-09

    申请人： Toshihiko Higuchi

    发明人： Toshihiko Higuchi

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L27/07 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L29/70

    CPC分类号： H01L29/7817 ,  H01L27/0722 ,  H01L29/42376 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66674 ,  H01L29/7302 ,  H01L29/7801

    摘要： A sidewall construction is utilized in the method of manufacture of semiconductor devices comprising planar type bipolar transistors wherein the width of the sidewall construction can be accuracy controlled which, in turn, controls accuracy the channel length of the base of the planar type bipolar transistors. This technique provides ways of preventing short circuiting between the formed transistor collector and emitter regions of the planar type bipolar transistors. The sidewall construction can also be employed in fabrication combination planar type bipolar/MIS type transistors resulting in higher density of these structures over the prior art laterally positioned structures.

    摘要翻译： 在制造包括平面型双极晶体管的半导体器件的方法中使用侧壁结构，其中侧壁结构的宽度可以被精确控制，这进而控制平面型双极晶体管的基极的沟道长度的精度。 该技术提供了防止形成的晶体管集电极与平面型双极晶体管的发射极区之间的短路的方法。 侧壁结构也可以用在制造组合平面型双极/ MIS型晶体管中，导致这些结构比现有技术的横向定位结构更高的密度。