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公开(公告)号：US20070272945A1
公开(公告)日：2007-11-29
申请号：US11709690
申请日：2007-02-23
申请人： Hisayoshi Matsuo , Tetsuzo Ueda
发明人： Hisayoshi Matsuo , Tetsuzo Ueda
IPC分类号： H01L29/772
CPC分类号： H01L29/7783 , H01L29/155 , H01L29/2003
摘要： A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer are broader than a forbidden bandwidth of the channel layer.
摘要翻译： 场效应晶体管具有所谓的双异质结构，其形成为使得电子行进的沟道层设置在电子供给层和衬垫层之间，其中衬垫层的禁带宽度和禁带宽度 的电子供应层比通道层的禁止带宽宽。
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公开(公告)号：US07687828B2
公开(公告)日：2010-03-30
申请号：US11709690
申请日：2007-02-23
申请人： Hisayoshi Matsuo , Tetsuzo Ueda
发明人： Hisayoshi Matsuo , Tetsuzo Ueda
IPC分类号： H01L31/072
CPC分类号： H01L29/7783 , H01L29/155 , H01L29/2003
摘要： A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer are broader than a forbidden bandwidth of the channel layer.
摘要翻译： 场效应晶体管具有所谓的双异质结构，其形成为使得电子行进的沟道层设置在电子供给层和衬垫层之间，其中衬垫层的禁带宽度和禁带宽度 的电子供应层比通道层的禁止带宽宽。
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公开(公告)号：US20070205407A1
公开(公告)日：2007-09-06
申请号：US11712482
申请日：2007-03-01
申请人： Hisayoshi Matsuo , Tatsuo Morita , Tetsuzo Ueda , Daisuke Ueda
发明人： Hisayoshi Matsuo , Tatsuo Morita , Tetsuzo Ueda , Daisuke Ueda
IPC分类号： H01L29/06
CPC分类号： H01L29/045 , H01L29/1029 , H01L29/2003 , H01L29/7787 , H01L33/007 , H01L33/0079 , H01L33/04 , H01L33/12
摘要： A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with a plurality of indentations whose plane orientations are the {0001} plane, and the plane orientation of the second principal surface is the {1-101} plane. The active layer is formed along the {1-101} plane.
摘要翻译： 氮化物半导体器件包括半导体层叠结构，其由具有第一主表面和与第一主表面相对并包括有源层的第二主表面的氮化物半导体形成。 半导体堆叠结构的第一主表面形成有多个平面取向为{0001}面并且第二主面的平面取向为{1-101}面的凹陷。 有源层沿{1-101}面形成。
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公开(公告)号：US20110297960A1
公开(公告)日：2011-12-08
申请号：US13213967
申请日：2011-08-19
CPC分类号： H01L29/7786 , H01L23/053 , H01L23/562 , H01L29/2003 , H01L29/225 , H01L29/452 , H01L29/475 , H01L2224/72 , H01L2924/01079 , H01L2924/12032 , H01L2924/00
摘要： A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.
摘要翻译： 晶体管组件的制造方法包括以下步骤：（a）形成晶体管; （b）抛光基底; 和（c）将基底基板抛光的晶体管固定到支撑基板上。 步骤（a）是在基底基板的主表面上形成第一半导体层和第二半导体层的工序。 步骤（b）是对基材的与主面相反的表面进行研磨的工序。 步骤（c）是在施加到基底基板上的应力存在下，使晶体管固定在支撑基板上，使基板的翘曲减小的方向。 基底由不同于第一半导体层和第二半导体层的材料制成，并且在第二半导体层上施加拉伸应力。
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公开(公告)号：US08450146B2
公开(公告)日：2013-05-28
申请号：US13213967
申请日：2011-08-19
IPC分类号： H01L21/00 , H01L21/338 , H01L21/331 , H01L21/8222 , H01L21/336
CPC分类号： H01L29/7786 , H01L23/053 , H01L23/562 , H01L29/2003 , H01L29/225 , H01L29/452 , H01L29/475 , H01L2224/72 , H01L2924/01079 , H01L2924/12032 , H01L2924/00
摘要： A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.
摘要翻译： 晶体管组件的制造方法包括以下步骤：（a）形成晶体管; （b）抛光基底; 和（c）将基底基板抛光的晶体管固定到支撑基板上。 步骤（a）是在基底基板的主表面上形成第一半导体层和第二半导体层的工序。 步骤（b）是对基材的与主面相反的表面进行研磨的工序。 步骤（c）是在施加到基底基板上的应力存在下，使晶体管固定在支撑基板上，使基板的翘曲减小的方向。 基底由不同于第一半导体层和第二半导体层的材料制成，并且在第二半导体层上施加拉伸应力。
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公开(公告)号：US20110278540A1
公开(公告)日：2011-11-17
申请号：US13111357
申请日：2011-05-19
IPC分类号： H01L29/12
CPC分类号： H01L29/7786 , H01L21/0237 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L29/1075 , H01L29/155 , H01L29/2003 , H01L29/475
摘要： Provided is a field-effect transistor which is capable of suppressing current collapse. An HEMT as the field-effect transistor includes: a first semiconductor layer made of a first nitride semiconductor; and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a greater band gap than a band gap of the first nitride semiconductor, wherein the first semiconductor layer includes a region in which a threading dislocation density increases in a stacking direction.
摘要翻译： 提供能够抑制电流塌陷的场效应晶体管。 作为场效应晶体管的HEMT包括：由第一氮化物半导体构成的第一半导体层; 以及第二半导体层，形成在所述第一半导体层上并且由具有比所述第一氮化物半导体的带隙大的带隙的第二氮化物半导体构成，其中所述第一半导体层包括其中穿透位错密度增加的区域 层叠方向
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公开(公告)号：US08013320B2
公开(公告)日：2011-09-06
申请号：US11712482
申请日：2007-03-01
申请人： Hisayoshi Matsuo , Tatsuo Morita , Tetsuzo Ueda , Daisuke Ueda
发明人： Hisayoshi Matsuo , Tatsuo Morita , Tetsuzo Ueda , Daisuke Ueda
IPC分类号： H01L31/00
CPC分类号： H01L29/045 , H01L29/1029 , H01L29/2003 , H01L29/7787 , H01L33/007 , H01L33/0079 , H01L33/04 , H01L33/12
摘要： A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with a plurality of indentations whose plane orientations are the {0001} plane, and the plane orientation of the second principal surface is the {1-101} plane. The active layer is formed along the {1-101} plane.
摘要翻译： 氮化物半导体器件包括半导体层叠结构，其由具有第一主表面和与第一主表面相对并包括有源层的第二主表面的氮化物半导体形成。 半导体堆叠结构的第一主表面形成有多个平面取向为{0001}面并且第二主面的平面取向为{1-101}面的凹陷。 有源层沿{1-101}面形成。
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