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公开(公告)号：US20190267065A1
公开(公告)日：2019-08-29
申请号：US16285549
申请日：2019-02-26
Applicant: Hitachi, Ltd.
Inventor： Masato HAYASHI , Masanao YAMAOKA
Abstract: The information processing apparatus is provided with a plurality of spin units for storing spin states and searching for a predetermined state by updating a spin state of a spin unit based on spin states of other spin units. The information processing apparatus includes: a first semiconductor integrated circuit device in which a plurality of first spin units are formed; a second semiconductor integrated circuit device in which a second spin unit is formed; an inter-chip wire connecting the first semiconductor integrated circuit device and the second semiconductor integrated circuit device; and a transmitter connection unit connected to the inter-chip wire and simultaneously shared by the plurality of first spin units. The transmitter connection unit transmits a spin state of a spin unit of which the spin state is changed among the plurality of first spin units, to the second semiconductor integrated circuit device through the inter-chip wire.
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公开(公告)号：US20190155330A1
公开(公告)日：2019-05-23
申请号：US15754614
申请日：2015-08-24
Applicant: HITACHI, LTD.
Inventor： Masanao YAMAOKA , Takeshi KATO , Chihiro YOSHIMURA , Masato HAYASHI
Abstract: An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer.
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公开(公告)号：US20200019885A1
公开(公告)日：2020-01-16
申请号：US16456174
申请日：2019-06-28
Applicant: Hitachi, Ltd.
Inventor： Takashi TAKEMOTO , Normann MERTIG , Masato HAYASHI
IPC: G06N20/00
Abstract: Provided is a more efficient method as a method of parameter adjustment of a graph embedded in an annealing machine. An information processing apparatus including an annealing calculation circuit including a plurality of spin units, which obtains a solution using an Ising model, is also provided. In the apparatus, each of the plurality of spin units includes a first memory cell that stores a value of the spin of the Ising model, a second memory cell that stores an interaction coefficient with an adjacent spin that interacts with the spins, a third memory cell that stores an external magnetic field coefficient of the spin, and an operational circuit that performs an operation of determining a next value of the spin based on a value of the adjacent spin, the interaction coefficient, and the external magnetic field coefficient. Further, the apparatus includes an external magnetic field coefficient update circuit that updates the external magnetic field coefficient with a monotonic increase or a monotonic decrease, and the annealing calculation circuit performs the annealing calculation a plurality of times by the operational circuit based on the updated external magnetic field coefficient.
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公开(公告)号：US20160063391A1
公开(公告)日：2016-03-03
申请号：US14645872
申请日：2015-03-12
Applicant: Hitachi, Ltd.
Inventor： Masato HAYASHI , Chihiro YOSHIMURA , Masanao YAMAOKA
CPC classification number: G06F7/588 , G06N7/005 , G06N99/00 , G06N99/002
Abstract: A highly-convenient information processing system capable of obtaining a solution of a problem under conditions desired by a user and a management apparatus capable of enhancing the convenience of the information processing system are suggested. An information processing system includes: a host unit equipped with one or more semiconductor chips that execute a ground-state search of an Ising model; and an operation unit that provides a user interface for a user to designate a problem; and a management unit that converts the problem designated by the user by using the user interface into the Ising model and controls the host unit to have the semiconductor chip perform the ground-state search of the converted Ising model; wherein the user can designate a condition for solving the problem by using the user interface; wherein the management unit generates an operating condition of the semiconductor chip according to the condition designated by the user and reports the generated operating condition and the Ising model of the problem designated by the user to the host unit; and wherein the host unit controls the semiconductor chip in accordance with the operating condition reported from the management unit.
Abstract translation: 提出一种能够在能够提高信息处理系统的便利性的用户和管理装置所期望的条件下获得问题的解决方案的高度方便的信息处理系统。 信息处理系统包括：配备有执行Ising模型的基态搜索的一个或多个半导体芯片的主机单元; 以及操作单元，其为用户提供用于指定问题的用户界面; 以及管理单元，其将用户指定的问题通过使用用户界面转换为Ising模型并且控制主机单元使半导体芯片执行对所转换的Ising模型的基态搜索; 其中所述用户可以通过使用所述用户界面来指定用于解决所述问题的条件; 其中，所述管理单元根据所述用户指定的条件生成所述半导体芯片的工作状态，并将所生成的操作条件和由所述用户指定的问题的所述Ising模型报告给所述主机单元; 并且其中所述主机单元根据从所述管理单元报告的操作条件来控制所述半导体芯片。
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公开(公告)号：US20180300287A1
公开(公告)日：2018-10-18
申请号：US15735033
申请日：2015-06-09
Applicant: HITACHI, LTD.
Inventor： Takuya OKUYAMA , Masanao YAMAOKA , Chihiro YOSHIMURA , Masato HAYASHI , Akihito AKAI
IPC: G06F17/10
Abstract: An information processing apparatus manufactured at low cost and with ease and that is capable of making a search for a ground state of an arbitrary Ising model. An information processing unit containing a plurality of semiconductor chips, each retains a value of one spin or values of a plurality of spins and simulates interactions among the spins, inter-chip wiring between the necessary semiconductor chips, and a control unit that cause each semiconductor chip to perform interaction computation. The control unit converts data of a problem into data of a lattice-shaped Ising model, which is possibly expressed by the plurality of semiconductor chips, without causing a spin arrangement, in a ground state of an Ising model for the problem, to be changed. The data of the lattice-shaped Ising model is divided for allocation to the plurality of semiconductor chips, and causes each semiconductor chip to perform the interaction computation.
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Patent Agency Ranking
公开(公告)号：US20160064099A1
公开(公告)日：2016-03-03
申请号：US14644906
申请日：2015-03-11
Applicant: Hitachi, Ltd.
Inventor： MASANAO YAMAOKA , Goichi ONO , Chihiro YOSHIMURA , Masato HAYASHI
CPC classification number: G11C29/08 , G06N7/005 , G06N99/002 , G11C29/76
Abstract: A semiconductor device capable of easily and properly detecting a defective element unit(s) and a quality management method for the semiconductor device are suggested. A semiconducting device simulating interactions between nodes in an interaction model is equipped with a quality management unit for managing the quality of each element unit provided corresponding to each node, wherein the quality management unit executes a specified quality test of each element unit, compares test results of the quality test with pre-given results to be obtained from the quality test, and detects a defective memory cell(s) and a defective element unit(s) based on the comparison results.
Abstract translation: 建议能够容易且适当地检测缺陷元件单元的半导体器件和半导体器件的质量管理方法。 模拟交互模型中节点之间的交互的半导体装置配备有用于管理对应于每个节点提供的每个元素单元的质量的质量管理单元，其中质量管理单元执行每个元素单元的指定质量测试，比较测试结果 的质量测试，并从质量测试中获得预先给定的结果，并且基于比较结果来检测有缺陷的存储单元和有缺陷的元件单元。
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公开(公告)号：US20160062951A1
公开(公告)日：2016-03-03
申请号：US14641578
申请日：2015-03-09
Applicant: HITACHI, LTD.
Inventor： Chihiro YOSHIMURA , Masato HAYASHI , Masanao YAMAOKA
CPC classification number: G06F17/18 , G06F7/58 , G06F7/588 , G06F2207/58 , G06N7/005 , G06N99/002 , G11C11/16 , G11C19/02 , G11C19/08 , G11C19/0875 , G11C19/0883 , H03K19/20
Abstract: A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin, a memory cell configured to store an external magnetic field coefficient of the spin, and an interaction circuit configured to determine a subsequent state of the spin. The spin units individually include a random number generator configured to supply the random number to the plurality of the spin units and generate two-valued simulated coefficients of two values or simulated coefficients of three values in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.
Abstract translation: 半导体器件包括多个自旋单元，其单独地包括被配置为存储Ising模型中的自旋值的存储器单元，被配置为存储来自在自旋上进行交互的相邻自旋的相互作用系数的存储单元，配置的存储单元 以存储旋转的外部磁场系数，以及配置为确定后续旋转状态的相互作用电路。 自旋单元分别包括随机数发生器，其被配置为向多个自旋单元提供随机数，并且在执行相互作用以产生自旋的后续状态时生成两个值或三个值的模拟系数的两值模拟系数 的自旋单位来自相邻旋转单元的自旋值，相互作用系数和外部磁场系数。
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公开(公告)号：US20130159513A1
公开(公告)日：2013-06-20
申请号：US13716415
申请日：2012-12-17
Applicant: HITACHI, LTD.
Inventor： Masato HAYASHI , Takeshi KATO , Yasuhiro ASA
IPC: H04L12/26
CPC classification number: H04L43/00 , H04L43/0817 , H04L43/50
Abstract: An object is to prevent overload on a shared resource. In an information processing system including a resource possibly shared between a plurality of work loads, an additional load is applied to the resource while operating the work loads, and the performances of the work loads are monitored.
Abstract translation: 一个对象是防止共享资源超载。 在包括可能在多个工作负载之间共享的资源的信息处理系统中，在操作工作负载的同时向资源施加额外的负载，并监视工作负载的性能。
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公开(公告)号：US20170185380A1
公开(公告)日：2017-06-29
申请号：US15324178
申请日：2014-07-09
Applicant: HITACHI, LTD.
Inventor： Masato HAYASHI , Masanao YAMAOKA , Chihiro YOSHIMURA
CPC classification number: G06F7/588 , G06F17/18 , G06N7/005 , G06N99/002 , G11C11/16 , H01L27/11 , H03L7/26
Abstract: A spin unit provided with a memory cell that stores a value of one spin of an Ising model, a memory cell that stores an interaction coefficient from an adjacent spin which interacts with the corresponding spin, a memory cell that stores an external magnetic field coefficient of the one spin and circuits that determine the next state of the one spin on the basis of a product of a value of each adjacent spin and the corresponding interaction coefficient and the external magnetic field coefficient is configured, the semiconductor device is provided with a spin array where the plural spin units are arranged and connected on a two-dimensional plane on a semiconductor substrate, a random number generator and a bit regulator, the bit regulator operates output of the random number generator and supplies a random bit to all spin units in the spin array via one wire.
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公开(公告)号：US20160065210A1
公开(公告)日：2016-03-03
申请号：US14638205
申请日：2015-03-04
Applicant: HITACHI, LTD.
Inventor： Chihiro YOSHIMURA , Masanao YAMAOKA , Masato HAYASHI
IPC: H03K19/00
CPC classification number: H03K19/0002 , G06N7/005 , G06N99/005 , G11C11/1659 , G11C11/5607
Abstract: An object of the present invention is to realize an example of configuration that approximately represents a state of quantum spin in a semiconductor device where components as a basic configuration unit are arrayed so as to search a ground state of Ising model. There is disclosed a semiconductor device provided with plural units each of which is equipped with a first memory cell that stores a value which represents one spin of the Ising model by three or more states, a second memory cell that stores an interaction coefficient showing interaction from another spin which exerts interaction on the one spin and a logical circuit that determines the next state of the one spin on the basis of a function having a value which represents a state of the other spin and the interaction coefficient as a constant or a variable.
Abstract translation: 本发明的目的是实现一种近似表示半导体装置中的量子自旋状态的配置示例，其中将作为基本配置单元的组件排列以搜索Ising模型的基态。 公开了一种设置有多个单元的半导体器件，每个单元配备有第一存储器单元，其存储表示Ising模型的一个自旋的值由三个或更多个状态，第二存储单元，其存储显示相互作用的相互作用系数 基于具有表示另一个自旋的状态的值的函数和作为常数或变量的相互作用系数的函数确定一个自旋的下一个状态的逻辑电路的另一自旋在一个自旋上发生相互作用。
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