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34 条记录 (耗时 0.02 秒)

    Hot-upgrade/hot-add memory
    4.
    发明授权
    Hot-upgrade/hot-add memory 失效
    热升级/热添加内存

    公开(公告)号：US06854070B2

    公开(公告)日：2005-02-08

    申请号：US09769978

    申请日：2001-01-25

    申请人： Jerome J. Johnson ,  John M. MacLaren ,  Robert A. Lester ,  John E. Larson ,  Gary J. Piccirillo ,  Christian H. Post ,  Jeffery Galloway ,  Ho M. Lai ,  Anisha Anand ,  Eric Rose

    发明人： Jerome J. Johnson ,  John M. MacLaren ,  Robert A. Lester ,  John E. Larson ,  Gary J. Piccirillo ,  Christian H. Post ,  Jeffery Galloway ,  Ho M. Lai ,  Anisha Anand ,  Eric Rose

    IPC分类号： G06F11/10 ,  G06F11/00

    CPC分类号： G06F11/108

    摘要： A method of adding memory capacity to a computer system. The computer system comprises a redundant memory system including a plurality of memory cartridges. By powering-down a memory cartridge, adding an additional memory module to the memory cartridge, and powering-up the memory cartridge for each memory cartridge in the system, the system can transition from a redundant mode of operation to a non-redundant mode of operation for each power-down, thus allowing the computer system to remain functional during the addition of the memory module. Alternatively, memory cartridges with higher memory capacity than those currently present in the computer system can be used to replace existing memory cartridges in the computer system, using the same techniques.

    摘要翻译： 一种向计算机系统增加内存容量的方法。 计算机系统包括包括多个存储器盒的冗余存储器系统。 通过关闭存储卡，将额外的内存模块添加到内存盒，并为系统中的每个内存盒启动内存盒，系统可以从冗余操作模式转换到非冗余模式 操作每个掉电，从而允许计算机系统在添加存储器模块期间保持功能。 或者，可以使用具有比当前存在于计算机系统中的存储器容量更高的存储器盒来替代计算机系统中的现有存储器盒，使用相同的技术。

    Memory latency and bandwidth optimizations
    7.
    发明授权
    Memory latency and bandwidth optimizations 失效

    公开(公告)号：US06938133B2

    公开(公告)日：2005-08-30

    申请号：US09965913

    申请日：2001-09-28

    申请人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    发明人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    IPC分类号： G06F13/16 ,  G06F12/00

    CPC分类号： G06F13/1642

    摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

    Memory auto-precharge
    8.
    发明授权
    Memory auto-precharge 有权
    内存自动预充电

    公开(公告)号：US06832286B2

    公开(公告)日：2004-12-14

    申请号：US10179081

    申请日：2002-06-25

    申请人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    发明人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    IPC分类号： G06F1200

    CPC分类号： G06F13/4243

    摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.

    摘要翻译： 计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。 该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。 为了最佳地运行到内存模块的反向循环，提供降级参数的技术，使得在系统执行请求时可以去除设计到存储器设备中的不必要的延迟。 通过消除任何不必要的延迟，可以提高周期时间和整体系统性能。

    Real-time hardware memory scrubbing
    9.
    发明授权
    Real-time hardware memory scrubbing 有权
    实时硬件内存擦除

    公开(公告)号：US06832340B2

    公开(公告)日：2004-12-14

    申请号：US09769959

    申请日：2001-01-25

    申请人： John E. Larson ,  John M. MacLaren ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jerome J. Johnson ,  Patrick L. Ferguson

    发明人： John E. Larson ,  John M. MacLaren ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jerome J. Johnson ,  Patrick L. Ferguson

    IPC分类号： G06F1100

    CPC分类号： G06F11/1076 ,  G06F11/106 ,  G06F2211/1088

    摘要： A system and technique for correcting data errors in a memory device. More specifically, data errors in a memory device are corrected by scrubbing the corrupted memory device. Generally, a host controller delivers a READ command to a memory controller. The memory controller receives the request and retrieves the data from a memory sub-system. The data is delivered to the host controller. If an error is detected, a scrub command is induced through the memory controller to rewrite the corrected data through the memory sub-system. Once a scrub command is induced, an arbiter schedules the scrub in the queue. Because a significant amount of time can occur before initial read in the scrub write back to the memory, an additional controller may be used to compare all subsequent READ and WRITE commands to those scrubs scheduled in the queue. If a memory location is rewritten with new data prior to scheduled scrub corresponding to the same address location, the controller will cancel the scrub to that particular memory location.

    摘要翻译： 一种用于校正存储器件中的数据错误的系统和技术。 更具体地，通过擦除损坏的存储器件来校正存储器件中的数据错误。 通常，主机控制器将READ命令传递给存储器控制器。 存储器控制器接收请求并从存储器子系统检索数据。 数据传送到主机控制器。 如果检测到错误，则通过存储器控制器感应擦除命令以通过存储器子系统重写校正的数据。 一旦引发了一个擦除命令，一个仲裁器会调度队列中的擦除。 因为在擦除写入内存之前的初始读取之前可能会发生大量时间，所以可以使用一个附加的控制器将所有后续的READ和WRITE命令与队列中调度的擦除进行比较。 如果在对应于相同地址位置的计划清除之前，用新数据重写存储器位置，则控制器将取消擦除该特定存储器位置。