公开(公告)号：US07046572B2

公开(公告)日：2006-05-16

申请号：US10250233

申请日：2003-06-16

申请人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

发明人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

IPC分类号： G11C7/00

CPC分类号： G11C5/143 ,  G11C8/08

摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：US07023758B2

公开(公告)日：2006-04-04

申请号：US11205565

申请日：2005-08-17

申请人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

发明人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

IPC分类号： G11C7/00

CPC分类号： G11C5/143 ,  G11C8/08

摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：US06768143B1

公开(公告)日：2004-07-27

申请号：US10604913

申请日：2003-08-26

申请人： Gregory J. Fredeman ,  John W. Golz ,  David R. Hanson ,  Hoki Kim

发明人： Gregory J. Fredeman ,  John W. Golz ,  David R. Hanson ,  Hoki Kim

IPC分类号： H01L2710

CPC分类号： H01L27/10897 ,  G11C11/4085

摘要： An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

摘要翻译： 提供了包括场效应晶体管（FET）的集成电路，其中栅极导通器具有设置在衬底的交替的源极和漏极区域之间的偶数个指状物。 手指在图案上设置有在水平方向上具有长度的区域的区域，该区域等于长度乘以由奇数手指占据的垂直方向上的宽度。

公开(公告)号：US06954387B2

公开(公告)日：2005-10-11

申请号：US10604375

申请日：2003-07-15

申请人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

发明人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

IPC分类号： G11C11/406 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

公开(公告)号：US06816397B1

公开(公告)日：2004-11-09

申请号：US10448776

申请日：2003-05-29

申请人： John W. Golz ,  David R. Hanson ,  Hoki Kim

发明人： John W. Golz ,  David R. Hanson ,  Hoki Kim

IPC分类号： G11C502

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093

摘要： As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.

摘要翻译： 如本文所公开的，提供集成电路存储器，其包括被耦合用于访问多个存储单元，第二读出放大器和输入/输出数据线对（IODL）的初级读出放大器，每个IODL对被耦合到主感测 放大器和每个IODL对承载表示存储位的互补信号。 存储器还包括成对的双向主数据线（BPDL），每个BPDL对被耦合到第二读出放大器，并且每个BPDL对适于承载表示存储位的其他互补信号。 本地缓冲器适于根据控制输入将IODL携带的互补信号传送到BPDL，反之亦然。

公开(公告)号：US07668003B2

公开(公告)日：2010-02-23

申请号：US12108548

申请日：2008-04-24

申请人： John E. Barth, Jr. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

发明人： John E. Barth, Jr. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

IPC分类号： G11C11/24

CPC分类号： H01L27/10829 ,  G11C7/02 ,  G11C11/4099 ,  H01L27/10861 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.

摘要翻译： 公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。 该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。 两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。 此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。 还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

公开(公告)号：US20060285411A1

公开(公告)日：2006-12-21

申请号：US11160273

申请日：2005-06-16

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C7/00

CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

摘要翻译： 具有与正常读取和写入操作交织的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

公开(公告)号：US07145829B1

公开(公告)日：2006-12-05

申请号：US11160273

申请日：2005-06-16

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： C11C7/00

CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

摘要翻译： 具有与正常读取和写入操作交错的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

公开(公告)号：US20130271181A1

公开(公告)日：2013-10-17

申请号：US13449018

申请日：2012-04-17

申请人： Hoki Kim ,  Changku Hwang ,  Jinuk Shin

发明人： Hoki Kim ,  Changku Hwang ,  Jinuk Shin

IPC分类号： H03K19/0175

CPC分类号： H03K19/017509 ,  G06F1/26

摘要： A system and method of shifting a data signal from a first voltage domain having a first logic level to a second voltage domain having a second logic level, the second logic level having a second logical high state greater than a first logical high state in the first logic level and a single power supply logic level shifter circuit having a single power supply source, an input node and an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain.

摘要翻译： 一种将数据信号从具有第一逻辑电平的第一电压域移位到具有第二逻辑电平的第二电压域的系统和方法，所述第二逻辑电平具有大于第一逻辑高状态的第二逻辑高状态 逻辑电平和具有单个电源，输入节点和输出节点的单个电源逻辑电平移位器电路，所述输入节点耦合到所述第一电压域中的发送器电路，并且所述输出节点耦合到所述第一电压源中的接收器电路 第二电压域，单个电源仅耦合到第二电压域中的单个电网。

公开(公告)号：US20090268510A1

公开(公告)日：2009-10-29

申请号：US12108548

申请日：2008-04-24

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

IPC分类号： G11C11/24 ,  H01L21/8242

CPC分类号： H01L27/10829 ,  G11C7/02 ,  G11C11/4099 ,  H01L27/10861 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.

摘要翻译： 公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。 该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。 两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。 此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。 还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。