公开(公告)号：US07023758B2

公开(公告)日：2006-04-04

申请号：US11205565

申请日：2005-08-17

申请人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

发明人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

IPC分类号： G11C7/00

CPC分类号： G11C5/143 ,  G11C8/08

摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：US07046572B2

公开(公告)日：2006-05-16

申请号：US10250233

申请日：2003-06-16

申请人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

发明人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

IPC分类号： G11C7/00

CPC分类号： G11C5/143 ,  G11C8/08

摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：US07194670B2

公开(公告)日：2007-03-20

申请号：US10708184

申请日：2004-02-13

申请人： Jonathan R. Fales ,  Gregory J. Fredeman ,  Kevin W. Gorman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Alan D. Norris ,  Paul C. Parries ,  Matthew R. Wordeman

发明人： Jonathan R. Fales ,  Gregory J. Fredeman ,  Kevin W. Gorman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Alan D. Norris ,  Paul C. Parries ,  Matthew R. Wordeman

IPC分类号： G01R31/28

CPC分类号： G11C29/16 ,  G11C29/12015 ,  G11C29/14 ,  G11C2029/0401

摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

公开(公告)号：US06294449B1

公开(公告)日：2001-09-25

申请号：US09447627

申请日：1999-11-23

申请人： Teresa J. Wu ,  Bomy A. Chen ,  John W. Golz ,  Charles W. Koburger, III ,  Paul C. Parries ,  Christopher J. Waskiewicz ,  Jin Jwang Wu

发明人： Teresa J. Wu ,  Bomy A. Chen ,  John W. Golz ,  Charles W. Koburger, III ,  Paul C. Parries ,  Christopher J. Waskiewicz ,  Jin Jwang Wu

IPC分类号： H01L2144

CPC分类号： H01L21/76897

摘要： A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.

摘要翻译： 一对共用共用电极的晶体管 DRAM阵列中的位线具有与位线的自对准接触，其中晶体管栅极堆叠仅具有具有氮化物覆盖层的多晶硅层; 用于位线接触的孔径被时间刻蚀以仅在栅极之间穿透而不到达硅衬底; 蚀刻栅极的暴露的氮化物肩部以暴露多晶硅; 通过选择性蚀刻去除层间电介质的其余部分; 暴露的聚合物被再氧化以保护浇口; 并清洁孔径底部; 从而不需要DRAM的厚栅堆叠，以便提高跨芯片的线宽的均匀性，超出了DRAM技术可以传送的范围。

公开(公告)号：US08716776B2

公开(公告)日：2014-05-06

申请号：US13533099

申请日：2012-06-26

申请人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

发明人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

IPC分类号： H01L29/12

CPC分类号： H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

公开(公告)号：US08395217B1

公开(公告)日：2013-03-12

申请号：US13283031

申请日：2011-10-27

申请人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/76289 ,  H01L21/823878 ,  H01L27/1203

摘要： A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.

摘要翻译： 提供了具有隔离区域的半导体器件结构及其制造方法。 半导体器件结构包括绝缘体上硅（SOI）衬底。 在SOI衬底上形成多个栅极。 半导体器件结构还包括形成在多个栅极中的每一个之间的具有侧壁的沟槽。 半导体器件结构还包括形成在沟槽中的外延横向生长层。 外延横向生长层从沟槽的相对侧壁横向生长，使得外延横向生长层包围延伸到SOI衬底中的沟槽的一部分。 外延横向生长层以这样的方式形成，使得其包括覆盖SOI衬底的掩埋介电层的气隙区域。

公开(公告)号：US08236632B2

公开(公告)日：2012-08-07

申请号：US12899635

申请日：2010-10-07

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

摘要翻译： 半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入 在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。 在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。 在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。 在其他示例性实施例中，没有接合对接。 在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

公开(公告)号：US20120187490A1

公开(公告)日：2012-07-26

申请号：US13426547

申请日：2012-03-21

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

公开(公告)号：US20110193193A1

公开(公告)日：2011-08-11

申请号：US12704084

申请日：2010-02-11

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US20080175085A1

公开(公告)日：2008-07-24

申请号：US12057011

申请日：2008-03-27

申请人： John Edward Barth ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

发明人： John Edward Barth ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

IPC分类号： G11C7/06

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。