公开(公告)号：US07593281B2

公开(公告)日：2009-09-22

申请号：US11781581

申请日：2007-07-23

申请人： Hong Beom Pyeon ,  Bruce Millar

发明人： Hong Beom Pyeon ,  Bruce Millar

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

摘要翻译： 适用于高速存储器件的降压转换器（VDC）。 VDC包括一个稳定的驱动器和有源驱动器以及至少一个额外的晶体管。 稳定的驱动器和有源驱动器在器件启动期间由晶体管开关耦合，以提供对工作电压和电流的快速上升。 启动后，稳定的驱动器和主动驱动功能保持稳定的工作电压和电流。 在发出表示存储器的读取，写入和/或刷新的活动命令时，附加晶体管被数字控制以驱动工作电压和电流。 以这种方式，附加晶体管对存储器阵列中的活动引起的工作电压和电流的波动提供快速补偿。

公开(公告)号：US08611171B2

公开(公告)日：2013-12-17

申请号：US13423901

申请日：2012-03-19

申请人： Hong Beom Pyeon ,  Bruce Millar

发明人： Hong Beom Pyeon ,  Bruce Millar

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

公开(公告)号：US07248531B2

公开(公告)日：2007-07-24

申请号：US11195641

申请日：2005-08-03

申请人： Hong Beom Pyeon ,  Bruce Millar

发明人： Hong Beom Pyeon ,  Bruce Millar

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

摘要翻译： 适用于高速存储器件的降压转换器（VDC）。 VDC包括一个稳定的驱动器和有源驱动器以及至少一个额外的晶体管。 稳定的驱动器和有源驱动器在器件启动期间由晶体管开关耦合，以提供对工作电压和电流的快速上升。 启动后，稳定的驱动器和主动驱动功能保持稳定的工作电压和电流。 在发出表示存储器的读取，写入和/或刷新的活动命令时，附加晶体管被数字控制以驱动工作电压和电流。 以这种方式，附加晶体管对存储器阵列中的活动引起的工作电压和电流的波动提供快速补偿。

公开(公告)号：US08164968B2

公开(公告)日：2012-04-24

申请号：US12505069

申请日：2009-07-17

申请人： Hong Beom Pyeon ,  Bruce Millar

发明人： Hong Beom Pyeon ,  Bruce Millar

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

摘要翻译： 适用于高速存储器件的降压转换器（VDC）。 VDC包括一个稳定的驱动器和有源驱动器以及至少一个额外的晶体管。 稳定的驱动器和有源驱动器在器件启动期间由晶体管开关耦合，以提供对工作电压和电流的快速上升。 启动后，稳定的驱动器和主动驱动功能保持稳定的工作电压和电流。 在发出表示存储器的读取，写入和/或刷新的活动命令时，附加晶体管被数字控制以驱动工作电压和电流。 以这种方式，附加晶体管对存储器阵列中的活动引起的工作电压和电流的波动提供快速补偿。

公开(公告)号：US08812768B2

公开(公告)日：2014-08-19

申请号：US12033577

申请日：2008-02-19

申请人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

摘要： A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

摘要翻译： 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

公开(公告)号：US08526260B2

公开(公告)日：2013-09-03

申请号：US13305064

申请日：2011-11-28

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C7/00

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

摘要： A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

公开(公告)号：US20130070547A1

公开(公告)日：2013-03-21

申请号：US13621486

申请日：2012-09-17

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C29/24

CPC分类号： G11C29/785 ,  G11C29/44 ,  G11C2029/1206 ,  G11C2029/4402

摘要： Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.

摘要翻译： 公开了可以包括包括第一冗余存储器元件，输入/输出接口，第一层保险丝盒和保险丝熔断控制的第一层的系统和方法。 这些系统和方法还可以包括通过包括耦合到第一冗余存储器元件的第二层存储器元件和第二层熔丝盒的第一连接耦合到第一层的第二层。 此外，这些系统和方法还可以包括耦合到第一层的冗余寄存器，其中当第二层存储器元件的一部分出现故障时，冗余寄存器向熔丝熔断控制提供信息，其分配第一冗余存储器的一部分 元件，以通过在第一层熔丝盒和第二层熔丝盒中吹入元件来为第二层存储元件的故障部分提供冗余。

公开(公告)号：US08363444B2

公开(公告)日：2013-01-29

申请号：US13365895

申请日：2012-02-03

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G11C7/02

CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

摘要翻译： 用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括用于连接至少一个分立存储器件的本地控制接口，用于连接至少一个分立存储器件的本地输入/输出接口以及全局输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US08300488B2

公开(公告)日：2012-10-30

申请号：US12705040

申请日：2010-02-12

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4061

摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

摘要翻译： 动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。 阵列的每个DRAM单元与相应列的相应行和位线的字线相连。 通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。 响应于自刷新模式信号产生的振荡电路产生基本时间段。 第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。 第二分频器/时间周期乘法器还根据与DRAM器件有关的温度变化因素来改变改变的时间周期。 在自刷新模式下，存储在DRAM单元中的数据被刷新。 根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

公开(公告)号：US20120069693A1

公开(公告)日：2012-03-22

申请号：US13305064

申请日：2011-11-28

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C5/14

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

摘要： A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

摘要翻译： 动态随机存取存储器（DRAM）可选择性地在睡眠模式和另一模式下操作。 DRAM具有在刷新模式下刷新的数据存储单元。 为DRAM的操作提供升压电压。 升压电压提供器包括一组电荷泵电路，其基于用于在睡眠模式下刷新DRAM单元中的数据的刷新时间由泵控制电路选择性地激活。