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11 条记录 (耗时 0.019 秒)

    Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
    4.
    发明授权
    Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures 有权
    用作半导体沟槽和通孔结构中的铜阻挡层的介电阻挡膜

    公开(公告)号：US07427563B2

    公开(公告)日：2008-09-23

    申请号：US11131003

    申请日：2005-05-16

    申请人： Hong-Qiang Lu ,  Peter A. Burke ,  Wilbur G. Catabay

    发明人： Hong-Qiang Lu ,  Peter A. Burke ,  Wilbur G. Catabay

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/02211 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02315 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3121 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

    摘要翻译： 本发明涉及改进的介电铜阻挡层和相关互连结构。 一种结构包括具有铜线的半导体衬底。 在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。 在绝缘层中形成开口以露出铜线的一部分。 绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。 形成铜塞以填充开口并与下面的铜互连结构电接触。 本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

    Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell
    6.
    发明授权
    Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell 失效
    用于集成电路结构的碳纳米管存储单元，其具有可拆卸侧面间隔件，以允许访问存储器单元和用于形成这种存储器单元的

    公开(公告)号：US06955937B1

    公开(公告)日：2005-10-18

    申请号：US10917551

    申请日：2004-08-12

    申请人： Peter A. Burke ,  Sey-Shing Sun ,  Hong-Qiang Lu

    发明人： Peter A. Burke ,  Sey-Shing Sun ,  Hong-Qiang Lu

    IPC分类号： G11C13/02 ,  H01L21/00 ,  H01L27/10

    CPC分类号： H01L27/10 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/16 ,  Y10S977/943

    摘要： A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers. A silicon oxide layer is deposited over the structure and also anisotropically etched forming silicon oxide sidewall spacers on the polysilicon sidewall spacers. The polysilicon is wet etched with an etchant selective to adjacent materials to remove the polysilicon sidewalls spacers and all of the polysilicon in the chambers. Silicon oxide is formed over the structure and into the upper portion of the openings to seal the now empty chambers. A passivation layer may then be formed.

    摘要翻译： 一种用于集成电路的碳纳米管存储单元，其中室被构造成电介质材料如氮化硅的层，直到第一电接触。 这个房间里充满了多晶硅。 在氮化硅层和室之上形成一层碳纳米管垫或带。 在纳米管条之上形成电介质材料，例如氧化物层，并被图案化以形成一个向下到带状层的上部腔室，以使带状物移动到上部腔室或下部腔室中。 然后，上部室充满多晶硅。 在氧化物层上形成氮化硅层，并且向下形成接触开口，并且填充有钨，然后将其图案化以形成金属线。 任何暴露的氮化硅被去除。 在钨线上形成多晶硅层，并进行各向异性蚀刻以去除水平表面上的多晶硅，但留下多晶硅侧壁间隔物。 在结构上沉积氧化硅层，并且还各向异性地蚀刻在多晶硅侧壁间隔物上形成氧化硅侧壁间隔物。 用对相邻材料选择性的蚀刻剂湿式蚀刻多晶硅以去除多晶硅侧壁间隔物和室中的所有多晶硅。 在结构上形成氧化硅并进入开口的上部，以密封现在的空腔。 然后可以形成钝化层。

    Methods and structure for forming copper barrier layers integral with semiconductor substrates structures
    8.
    发明授权
    Methods and structure for forming copper barrier layers integral with semiconductor substrates structures 有权
    用于形成与半导体衬底结构成一体的铜阻挡层的方法和结构

    公开(公告)号：US07646077B2

    公开(公告)日：2010-01-12

    申请号：US12191171

    申请日：2008-08-13

    申请人： Hong-Qiang Lu ,  Peter A. Burke ,  Wilbur G. Catabay

    发明人： Hong-Qiang Lu ,  Peter A. Burke ,  Wilbur G. Catabay

    IPC分类号： H01L23/58 ,  H01L21/4763

    CPC分类号： H01L21/02211 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02315 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3121 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

    摘要翻译： 本发明涉及改进的介电铜阻挡层和相关互连结构。 一种结构包括具有铜线的半导体衬底。 在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。 在绝缘层中形成开口以露出铜线的一部分。 绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。 形成铜塞以填充开口并与下面的铜互连结构电接触。 本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

    Method and structure for forming dielectric layers having reduced dielectric constants
    10.
    发明授权
    Method and structure for forming dielectric layers having reduced dielectric constants 有权
    用于形成具有降低的介电常数的介电层的方法和结构

    公开(公告)号：US06774057B1

    公开(公告)日：2004-08-10

    申请号：US10180661

    申请日：2002-06-25

    申请人： Hong-Qiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay

    发明人： Hong-Qiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay

    IPC分类号： H01L2131

    CPC分类号： H01L21/02126 ,  H01L21/02203 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/312 ,  H01L21/31695 ,  H01L21/7682

    摘要： The present invention is directed to a semiconductor structure including a semiconductor substrate having at least one overlying layer formed thereon. The at least one overlying layer including at least one layer of dielectric material. The at least one layer of dielectric material including a protected region having a first dielectric constant and another porous region having a second dielectric constant wherein the value for the second dielectric constant is less than the first dielectric constant. The porous region having been formed by the implantation of a porosity inducing material into the porous region and subsequent annealing. A method for forming such structures is also included.

    摘要翻译： 本发明涉及包括其上形成有至少一个上覆层的半导体衬底的半导体结构。 所述至少一个覆盖层包括至少一层电介质材料。 所述至少一层介电材料包括具有第一介电常数的保护区和具有第二介电常数的另一多孔区，其中所述第二介电常数的值小于所述第一介电常数。 已经通过将孔隙率诱导材料注入多孔区域并随后进行退火而形成多孔区域。 还包括形成这种结构的方法。