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    Pulse-width control loop for clock with pulse-width ratio within wide range
    1.
    发明授权
    Pulse-width control loop for clock with pulse-width ratio within wide range 有权
    时钟脉冲宽度控制回路，脉宽范围宽

    公开(公告)号：US07466177B2

    公开(公告)日：2008-12-16

    申请号：US11491159

    申请日：2006-07-24

    申请人： Hong-Yi Huang ,  Wei-Ming Chiu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Wei-Ming Chiu ,  Yuan-Hua Chu

    IPC分类号： H03K3/17

    CPC分类号： H03K5/151 ,  H03K5/1565

    摘要： A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

    摘要翻译： 提供了在宽范围内具有任何脉冲宽度比的时钟的脉冲宽度控制回路（PWCL）。 采用差分可编程电荷泵通过互补连接来稳定电流源。 差分可编程电荷泵具有一对差动电荷泵和电流源模块，用于调节充放电比例，从而加快输出时钟可调脉宽比的范围，提高输出分辨率。 此外，采用无竞争的输入控制级以简化电路设计并避免静态功耗。 此外，控制级在一个周期调节上升脉冲宽度和下降脉冲宽度，从而加速锁定速度和输入时钟的可调脉冲宽度比（即占空比）的范围。

    Pulse-width control loop for clock with pulse-width ratio within wide range
    2.
    发明申请
    Pulse-width control loop for clock with pulse-width ratio within wide range 有权
    时钟脉冲宽度控制回路，脉宽范围宽

    公开(公告)号：US20070146025A1

    公开(公告)日：2007-06-28

    申请号：US11491159

    申请日：2006-07-24

    申请人： Hong-Yi Huang ,  Wei-Ming Chiu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Wei-Ming Chiu ,  Yuan-Hua Chu

    IPC分类号： H03L7/06

    CPC分类号： H03K5/151 ,  H03K5/1565

    摘要： A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

    摘要翻译： 提供了在宽范围内具有任何脉冲宽度比的时钟的脉冲宽度控制回路（PWCL）。 采用差分可编程电荷泵通过互补连接来稳定电流源。 差分可编程电荷泵具有一对差动电荷泵和电流源模块，用于调节充放电比例，从而加快输出时钟可调脉宽比的范围，提高输出分辨率。 此外，采用无竞争的输入控制级以简化电路设计并避免静态功耗。 此外，控制级在一个周期调节上升脉冲宽度和下降脉冲宽度，从而加速锁定速度和输入时钟的可调脉冲宽度比（即占空比）的范围。

    High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same
    3.
    发明申请
    High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same 有权
    高分辨率变容二极管，单边缘触发数字控制振荡器和使用相同的全数字锁相环

    公开(公告)号：US20110068841A1

    公开(公告)日：2011-03-24

    申请号：US12923435

    申请日：2010-09-21

    申请人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0991 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00071 ,  H03K2005/00293 ,  H03L2207/50

    摘要： A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

    摘要翻译： 数字控制振荡器（DCO）包括脉冲发生器，用于在触发信号的边沿产生脉冲信号，以及至少一个延迟电路，其被连接以延迟由脉冲发生器产生的脉冲信号。 脉冲发生器被耦合以接收来自至少一个延迟电路的延迟脉冲信号中的一个和使能信号作为触发信号。 数字控制变容二极管（DCV）包括具有栅极，源极，漏极和衬底的晶体管，其中栅极，源极，漏极和衬底中的至少一个被耦合以接收两个或更多个中的一个 电压，其中所述两个或更多个电压中的至少一个不是电源电压或接地。

    High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same
    4.
    发明授权
    High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same 有权
    高分辨率变容二极管，单边缘触发数字控制振荡器和使用相同的全数字锁相环

    公开(公告)号：US07859343B2

    公开(公告)日：2010-12-28

    申请号：US11595972

    申请日：2006-11-13

    申请人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

    IPC分类号： H03L7/08

    CPC分类号： H03L7/0991 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00071 ,  H03K2005/00293 ,  H03L2207/50

    摘要： A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

    摘要翻译： 数字控制振荡器（DCO）包括脉冲发生器，用于在触发信号的边沿产生脉冲信号，以及至少一个延迟电路，其被连接以延迟由脉冲发生器产生的脉冲信号。 脉冲发生器被耦合以接收来自至少一个延迟电路的延迟脉冲信号中的一个和使能信号作为触发信号。 数字控制变容二极管（DCV）包括具有栅极，源极，漏极和衬底的晶体管，其中栅极，源极，漏极和衬底中的至少一个被耦合以接收两个或更多个中的一个 电压，其中所述两个或更多个电压中的至少一个不是电源电压或接地。

    High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same
    5.
    发明申请
    High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same 有权
    高分辨率变容二极管，单边缘触发数字控制振荡器和使用相同的全数字锁相环

    公开(公告)号：US20080111641A1

    公开(公告)日：2008-05-15

    申请号：US11595972

    申请日：2006-11-13

    申请人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

    IPC分类号： H03L7/08 ,  H01L29/94 ,  H03B28/00

    CPC分类号： H03L7/0991 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00071 ,  H03K2005/00293 ,  H03L2207/50

    摘要： A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

    摘要翻译： 数字控制振荡器（DCO）包括脉冲发生器，用于在触发信号的边沿产生脉冲信号，以及至少一个延迟电路，其被连接以延迟由脉冲发生器产生的脉冲信号。 脉冲发生器被耦合以接收来自至少一个延迟电路的延迟脉冲信号中的一个和使能信号作为触发信号。 数字控制变容二极管（DCV）包括具有栅极，源极，漏极和衬底的晶体管，其中栅极，源极，漏极和衬底中的至少一个被耦合以接收两个或更多个中的一个 电压，其中所述两个或更多个电压中的至少一个不是电源电压或接地。

    BULK INPUT CURRENT SWITCH LOGIC CIRCUIT
    6.
    发明申请
    BULK INPUT CURRENT SWITCH LOGIC CIRCUIT 有权
    大容量输入电流开关逻辑电路

    公开(公告)号：US20090212822A1

    公开(公告)日：2009-08-27

    申请号：US12141112

    申请日：2008-06-18

    申请人： Hong-Yi Huang ,  Chun-Tsai Hung ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Chun-Tsai Hung ,  Yuan-Hua Chu

    IPC分类号： H03K19/094

    CPC分类号： H03K19/086 ,  H03K19/20

    摘要： A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

    摘要翻译： 公开了一种电流开关逻辑电路。 该电路包括由第一晶体管至第五晶体管形成的电流检测放大器和逻辑树。 逻辑树用于生成第一个电流和第二个电流。 电流检测放大器根据第一电流和第二电流产生第一输出信号和第二输出信号。

    Cycle time to digital converter
    7.
    发明授权
    Cycle time to digital converter 失效
    循环时间到数字转换器

    公开(公告)号：US07522084B2

    公开(公告)日：2009-04-21

    申请号：US11826339

    申请日：2007-07-13

    申请人： Hong-Yi Huang ,  Sheng-Dar Wu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Sheng-Dar Wu ,  Yuan-Hua Chu

    IPC分类号： H03M1/60

    CPC分类号： G04F10/005

    摘要： A cycle time to digital converter includes a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.

    摘要翻译： 数字转换器的周期时间包括双延迟锁定环路，多相采样检测器和VDL采样检测器。 双延迟锁定环路产生对应于第一延迟时间的第一电压和对应于第二延迟时间的第二电压。 多相采样检测器接收第一起始信号，第一停止信号和第一电压以检测粗延迟时间，根据粗延迟时间产生第一组信号，将第一停止信号延迟公共延迟时间以产生第二停止 并且将第一起始信号延迟粗延迟时间和公共延迟时间以产生第二起始信号。 VDL采样检测器接收第一电压，第二电压，第二起始信号和第二停止信号，用于检测精细的延迟时间，并根据微小的延迟时间产生第二组信号。

    DIFFERENTIAL BIDIRECTIONAL TRANSCEIVER AND RECEIVER THEREIN
    8.
    发明申请
    DIFFERENTIAL BIDIRECTIONAL TRANSCEIVER AND RECEIVER THEREIN 失效
    差分双向收发器和接收器

    公开(公告)号：US20080116936A1

    公开(公告)日：2008-05-22

    申请号：US11747921

    申请日：2007-05-14

    申请人： Hong-Yi Huang ,  Ruei-Iun Pu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Ruei-Iun Pu ,  Yuan-Hua Chu

    IPC分类号： H04L5/14 ,  H03K19/094

    CPC分类号： H03K19/094 ,  H03K19/018528 ,  H04L5/1423

    摘要： A differential bidirectional transceiver is provided. The differential bidirectional transceiver includes a first current transmitter, a second current transmitter and a receiver. The first current transmitter and the second current transmitter are coupled to a first interconnection and a second interconnection, respectively. Each of the current transmitters includes two current sources and two switches. The receiver includes an input circuit consisting of four differential pairs, a current summation circuit and a buffer.

    摘要翻译： 提供差分双向收发器。 差分双向收发器包括第一电流发射器，第二电流发射器和接收器。 第一电流发射器和第二电流发射器分别耦合到第一互连和第二互连。 每个电流变送器包括两个电流源和两个开关。 接收机包括由四个差分对，电流求和电路和缓冲器组成的输入电路。

    Bidirectional current-mode transceiver
    9.
    发明申请
    Bidirectional current-mode transceiver 失效
    双向电流模式收发器

    公开(公告)号：US20070132483A1

    公开(公告)日：2007-06-14

    申请号：US11442302

    申请日：2006-05-30

    申请人： Hong-Yi Huang ,  Ching-Chieh Wu ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Ching-Chieh Wu ,  Yuan-Hua Chu

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018592 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298

    摘要： A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus improving operating speed. Therefore, the provided transceiver can be applied to a long transmission line.

    摘要翻译： 提供了一种双向电流模式收发器，用于以当前信号传输的方式改善传输线上的传输速率，并且通过使用终端电阻来减少传输线上的电压信号的摆动，从而提高操作速度。 因此，所提供的收发器可以应用于长传输线。

    Onion waveform generator and spread spectrum clock generator using the same
    10.
    发明授权
    Onion waveform generator and spread spectrum clock generator using the same 有权
    洋葱波形发生器和扩频时钟发生器使用相同

    公开(公告)号：US08269536B2

    公开(公告)日：2012-09-18

    申请号：US12871920

    申请日：2010-08-31

    申请人： Hong-Yi Huang ,  Chih-Yuan Hsu ,  Wei-Sheng Tseng ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

    发明人： Hong-Yi Huang ,  Chih-Yuan Hsu ,  Wei-Sheng Tseng ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

    IPC分类号： H03L7/06

    CPC分类号： H04B1/69 ,  G06F1/022 ,  H03L7/197

    摘要： An onion waveform generator and a spread spectrum clock generator (SSCG) using the same are provided. The onion waveform generator includes a value generation unit and an accumulating unit. The value generation unit outputs a counting value. The accumulating unit accumulates the counting value to output a waveform value. The accumulating unit switches from an increasing mode to a decreasing mode if the waveform value is a third boundary value, and the accumulating unit switches from the decreasing mode to the increasing mode if the waveform value is a fourth boundary value.

    摘要翻译： 提供了洋葱波形发生器和使用它的扩频时钟发生器（SSCG）。 洋葱波形发生器包括值生成单元和累积单元。 值产生单元输出计数值。 累加单元积累计数值，输出波形值。 如果波形值是第三边界值，则累加单元从增加模式切换到减小模式，并且如果波形值是第四边界值，则累加单元从递减模式切换到增加模式。