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    Apparatus and methods for forward error correction decoding
    1.
    发明申请
    Apparatus and methods for forward error correction decoding 失效
    用于前向纠错解码的装置和方法

    公开(公告)号：US20050060632A1

    公开(公告)日：2005-03-17

    申请号：US10660361

    申请日：2003-09-11

    申请人： Hooman Honary ,  Kumar Ganapathy ,  Amit Gupta ,  Siva Simanapalli

    发明人： Hooman Honary ,  Kumar Ganapathy ,  Amit Gupta ,  Siva Simanapalli

    IPC分类号： H03M13/03 ,  H03M13/41

    CPC分类号： H03M13/6502 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/6511

    摘要： An apparatus includes an instruction decoder, at least one control register coupled to the instruction decoder, and an add-compare-select (ACS) engine coupled to the at least one control register. The instruction decoder is operative to control the ACS engine to perform Viterbi decoding in response to the instruction decoder receiving a first instruction, and is operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a second instruction.

    摘要翻译： 一种装置包括指令解码器，耦合到指令解码器的至少一个控制寄存器以及耦合到至少一个控制寄存器的加法比较选择（ACS）引擎。 指令解码器可操作以响应于指令解码器接收第一指令来控制ACS引擎执行维特比解码，并且可操作以响应于指令解码器接收第二指令来控制ACS引擎执行turbo解码。

    Apparatus and methods for forward error correction decoding
    2.
    发明授权
    Apparatus and methods for forward error correction decoding 失效
    用于前向纠错解码的装置和方法

    公开(公告)号：US07159169B2

    公开(公告)日：2007-01-02

    申请号：US10660361

    申请日：2003-09-11

    申请人： Hooman Honary ,  Kumar Ganapathy ,  Amit R. Gupta ,  Siva Simanapalli

    发明人： Hooman Honary ,  Kumar Ganapathy ,  Amit R. Gupta ,  Siva Simanapalli

    IPC分类号： H03M13/03

    CPC分类号： H03M13/6502 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/6511

    摘要： An apparatus includes an instruction decoder, at least one control register coupled to the instruction decoder, and an add-compare-select (ACS) engine coupled to the at least one control register. The instruction decoder is operative to control the ACS engine to perform Viterbi decoding in response to the instruction decoder receiving a first instruction, and is operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a second instruction.

    摘要翻译： 一种装置包括指令解码器，耦合到指令解码器的至少一个控制寄存器以及耦合到至少一个控制寄存器的加法比较选择（ACS）引擎。 指令解码器可操作以响应于指令解码器接收第一指令来控制ACS引擎执行维特比解码，并且可操作以响应于指令解码器接收第二指令来控制ACS引擎执行turbo解码。

    Methods for a random read and read/write block accessible memory
    4.
    发明授权
    Methods for a random read and read/write block accessible memory 有权
    随机读取和写入块可访问存储器的方法

    公开(公告)号：US08745314B1

    公开(公告)日：2014-06-03

    申请号：US12490930

    申请日：2009-06-24

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F13/1694 ,  G06F2212/211

    摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

    摘要翻译： 在本发明的一个实施例中，公开了一种存储装置。 存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。 存储器阵列是块读/写可访问和随机读取可访问的。 块读/写控制器耦合在存储器阵列和外部互连之间。 块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。 随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。 随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

    METHODS FOR TWO-DIMENSIONAL MAIN MEMORY
    5.
    发明申请
    METHODS FOR TWO-DIMENSIONAL MAIN MEMORY 有权
    二维主记忆的方法

    公开(公告)号：US20140075101A1

    公开(公告)日：2014-03-13

    申请号：US14016218

    申请日：2013-09-02

    申请人： Vijay Karamcheti ,  Kumar Ganapathy

    发明人： Vijay Karamcheti ,  Kumar Ganapathy

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G11C5/04 ,  G11C29/76

    摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

    摘要翻译： 在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。 存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。 从存储器控制器从地址控制器接收存储器模块的存储器访问请求。 从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

    METHODS OF A SERVER WITH A TWO-DIMENSIONAL MAIN MEMORY
    6.
    发明申请
    METHODS OF A SERVER WITH A TWO-DIMENSIONAL MAIN MEMORY 审中-公开
    具有二维主存储器的服务器的方法

    公开(公告)号：US20140074880A1

    公开(公告)日：2014-03-13

    申请号：US14016223

    申请日：2013-09-03

    申请人： Vijay Karamcheti ,  Kumar Ganapathy

    发明人： Vijay Karamcheti ,  Kumar Ganapathy

    IPC分类号： G06F17/30

    CPC分类号： G11C16/0408 ,  G06F7/78 ,  G06F12/0207 ,  G06F12/0246 ,  G06F12/0607 ,  G06F16/2455 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/06 ,  Y02D10/13

    摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

    摘要翻译： 在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。 存储器模块的多个存储器片中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。 从存储器控制器从地址控制器接收存储器模块的存储器访问请求。 从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

    METHOD AND APPARATUS FOR DISTRIBUTED DIRECT MEMORY ACCESS FOR SYSTEMS ON CHIP
    7.
    发明申请
    METHOD AND APPARATUS FOR DISTRIBUTED DIRECT MEMORY ACCESS FOR SYSTEMS ON CHIP 有权
    用于芯片系统的分布式直接存储器访问的方法和装置

    公开(公告)号：US20130138877A1

    公开(公告)日：2013-05-30

    申请号：US13754505

    申请日：2013-01-30

    申请人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

    发明人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

    IPC分类号： G11C7/10 ,  G06F12/08

    CPC分类号： H04L49/90 ,  G06F12/08 ,  G06F13/28 ,  G06F2213/0038 ,  G11C7/1072

    摘要： A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

    摘要翻译： 在片上系统（SOC）中提供分布式直接存储器访问（DMA）方法，装置和系统。 DMA控制器单元被分配到各种需要直接存储器访问的功能模块。 功能模块与直接存储器访问发生的系统总线接口。 将期望直接存储器访问的全局缓冲存储器耦合到系统总线。 总线仲裁器用于仲裁哪些功能模块可以访问系统总线来执行直接存储器访问。 一旦由总线仲裁器选择功能模块来访问系统总线，它就可以建立与全局缓冲存储器的DMA程序。

    Writing to asymmetric memory
    8.
    发明授权
    Writing to asymmetric memory 有权
    写入不对称记忆

    公开(公告)号：US08266407B2

    公开(公告)日：2012-09-11

    申请号：US13053371

    申请日：2011-03-22

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

    摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

    摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。