公开(公告)号：US4542309A

公开(公告)日：1985-09-17

申请号：US468447

申请日：1983-02-22

申请人： Wilfried Klein ,  Erich Klink ,  Knut Najmann ,  Friedrich Wernicke

发明人： Wilfried Klein ,  Erich Klink ,  Knut Najmann ,  Friedrich Wernicke

IPC分类号： H03K3/286 ,  H03K3/287 ,  H03K19/20 ,  H03K5/22 ,  H03K17/56

CPC分类号： H03K3/287

摘要： Disclosed is a phase splitter with integrated latch circuit, where the complementary output signals generated after an input signal applied to a true-complement generator are available directly without any load by the latch circuit, where upon a premature change of the input signal there is no undesired change of the previously set switching state or of the output signals, respectively, and where a simple clocking for functional control can be used. The advantages presented by the disclosed Phase splitter substantially consist in that the speed with which the complementary output signals are supplied is extremely high since the output signals are available directly, i.e. with only one stage delay, the latch circuit being non-conductive in the stationary state, and thus in a latching process does not have to be switched from one stage to the other, but only switched on.

摘要翻译： 公开了一种具有集成锁存电路的分相器，其中在输入信号施加到真互补发生器之后产生的互补输出信号可直接获得，而锁存电路不需要任何负载，其中当输入信号的过早变化 分别预先设定的开关状态或输出信号的不期望的变化，以及可以使用用于功能控制的简单时钟。 所公开的相位分离器所呈现的优点基本上在于，互补输出信号的供给速度非常高，因为输出信号可以直接获得，即只有一级延迟，锁存电路在静态中是不导通的 状态，因此在锁定过程中不必从一个阶段切换到另一个阶段，而是仅被接通。

公开(公告)号：US4122548A

公开(公告)日：1978-10-24

申请号：US840457

申请日：1977-10-07

申请人： Klaus Heuber ,  Wilfried Klein ,  Knut Najmann ,  Friedrich Wernicke ,  Siegfried Kurt Wiedmann

发明人： Klaus Heuber ,  Wilfried Klein ,  Knut Najmann ,  Friedrich Wernicke ,  Siegfried Kurt Wiedmann

IPC分类号： G11C11/41 ,  G11C7/04 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C11/40

CPC分类号： G11C11/416 ,  G11C11/4113

摘要： A memory storage system which utilizes semiconductor storage cells comprised of cross-coupled bipolar transistors arranged in a memory system array with an error reference circuit and a standby reference circuit that is controlled by a clock signal. The standby reference circuit and the error reference circuit are both coupled to the bit lines and selectively control a restore circuit that maintains, in the standby state, a selected potential on the bit lines such that short access times are realized and current is prevented from flowing into unselected cells when adjacent defective cells are being read or written.

摘要翻译： 一种存储器存储系统，其利用布置在存储器系统阵列中的交叉耦合双极晶体管构成的半导体存储单元，其具有由时钟信号控制的误差参考电路和备用参考电路。 待机参考电路和误差参考电路都耦合到位线，并选择性地控制恢复电路，其在待机状态下保持位线上的选定电位，使得实现短访问时间并防止电流流动 当读取或写入相邻的有缺陷的单元时，进入未选择的单元格。

公开(公告)号：US4170017A

公开(公告)日：1979-10-02

申请号：US889169

申请日：1978-03-23

申请人： Wilfried Klein ,  Erich Klink ,  Volker Rudolph ,  Friedrich Wernicke

发明人： Wilfried Klein ,  Erich Klink ,  Volker Rudolph ,  Friedrich Wernicke

IPC分类号： G11C11/41 ,  G11C11/414 ,  G11C11/416 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H01L27/07 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L27/0788 ,  G11C11/416

摘要： In an integrated circuit an improved highly integrated semiconductor structure for providing a Schottky diode-resistor circuit configuration is disclosed. Although not limited thereto, the improved highly integrated semiconductor structure has particular utility when employed in a monolithic memory.

公开(公告)号：US4397002A

公开(公告)日：1983-08-02

申请号：US179581

申请日：1980-08-21

申请人： Rudolf Brosch ,  Helmut H. Heimeier ,  Wilfried Klein ,  Friedrich Wernicke

发明人： Rudolf Brosch ,  Helmut H. Heimeier ,  Wilfried Klein ,  Friedrich Wernicke

IPC分类号： G11C11/41 ,  G11C11/411 ,  G11C11/416 ,  G11C7/00

CPC分类号： G11C11/4113

摘要： After a controlled strong lowering of the word line potential for the purpose of addressing a cell, said potential is immediately recharged simultaneously increasing the potential on the N side of the two PNP injectors of the cell and causing the injector capacitances of the selected storage cells and the bit line capacitances to form a capacitive voltage divider, so that the bit lines connected thereto are recharged to different degrees by the different magnitudes of the injector capacitances. Thus, the differential signal formed on the bit lines is noticeably amplified by the supply of currents of different magnitudes.

摘要翻译： 在用于寻址单元的目的电位的受控强降低之后，所述电位立即再充电，同时增加电池的两个PNP注入器的N侧上的电位，并导致所选择的存储单元的注入器电容和 位线电容以形成电容分压器，使得连接到其上的位线被不同程度地通过注射器电容的不同大小进行再充电。 因此，通过不同幅度的电流的供给，在位线上形成的差分信号被显着地放大。

公开(公告)号：US5798975A

公开(公告)日：1998-08-25

申请号：US782204

申请日：1997-01-10

申请人： Stefan Buttner ,  Jurgen Pille ,  Dieter Wendel ,  Friedrich Wernicke

发明人： Stefan Buttner ,  Jurgen Pille ,  Dieter Wendel ,  Friedrich Wernicke

IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C13/00

CPC分类号： G11C11/419

摘要： A new method is indicated for the restore of bitlines and data-lines from memory-cells. All bit- and datalines are switched together during the restore activity so that all restore-FETs can be prepared with the necessary re-charging current. The non-addressed bitlines are then switched off through their bitswitches. In this manner, the dimensions of the re-charging devices can be considerably reduced.

摘要翻译： 指示用于从存储单元恢复位线和数据线的新方法。 在恢复活动期间，所有位和数据都被切换到一起，以便所有恢复FET可以用必要的再充电电流进行准备。 然后通过它们的位开关关闭非寻址位线。 以这种方式，可以显着地减少再充电装置的尺寸。

公开(公告)号：US5615168A

公开(公告)日：1997-03-25

申请号：US538085

申请日：1995-10-02

申请人： George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

发明人： George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.

摘要翻译： 用于提供组合同步和自复位技术的存储器系统的单时钟周期流水线访问的方法和装置包括排列成列和行并由位线和字线相互配合的存储器单元阵列。 存储器系统还包括地址解码器和感测使能电路。 地址解码器在接收到地址后，解释地址以启用特定字线或字线，并禁止位线或位线的预充电。 当字线有效时，当时钟信号遇到过渡沿或处于活动状态时，感测使能电路产生检测使能信号。 当感测使能信号有效时，读出放大器通过位线从寻址的存储单元读取数据，以产生输出数据。