公开(公告)号：US08416121B2

公开(公告)日：2013-04-09

申请号：US12963314

申请日：2010-12-08

申请人： Howard H. Chen ,  Kai D. Feng ,  Duixian Liu

发明人： Howard H. Chen ,  Kai D. Feng ,  Duixian Liu

IPC分类号： G01S7/28

CPC分类号： G01S13/34 ,  G01S13/584 ,  G01S13/931 ,  G01S2007/358

摘要： A frequency modulation continuous wave (FMCW) system includes a first memory receiving a clock signal and storing voltage digital values of I FMCW signals, a second memory receiving the clock signal and storing the voltage digital values of the Q FMCW signals, a first digital-to-analog converter (DAC) connected to the first memory and receiving the clock signal for converting the voltage digital values of the I FMCW signal to a first analog voltage, a second digital-to-analog converter (DAC) connected to the second memory and receiving the clock signal for converting the voltage digital values of the Q FMCW signal to a second analog voltage, an I low-pass filter connected to the first DAC smoothing the I FMCW signal and a Q low-pass filter connected to the second DAC smoothing the Q FMCW signal.

摘要翻译： 频率调制连续波（FMCW）系统包括接收时钟信号并存储I FMCW信号的电压数字值的第一存储器，接收时钟信号并存储Q FMCW信号的电压数字值的第二存储器，第一数字 - 模拟转换器（DAC），连接到第一存储器并且接收用于将I FMCW信号的电压数字值转换为第一模拟电压的时钟信号;连接到第二存储器的第二数模转换器（DAC） 并接收用于将Q FMCW信号的电压数字值转换为第二模拟电压的时钟信号，连接到第一DAC的I低通滤波器平滑I FMCW信号和连接到第二DAC的Q低通滤波器 平滑Q FMCW信号。

公开(公告)号：US20120146845A1

公开(公告)日：2012-06-14

申请号：US12963314

申请日：2010-12-08

申请人： Howard H. Chen ,  Kai D. Feng ,  Duixian Liu

发明人： Howard H. Chen ,  Kai D. Feng ,  Duixian Liu

IPC分类号： G01S13/34

CPC分类号： G01S13/34 ,  G01S13/584 ,  G01S13/931 ,  G01S2007/358

摘要： A frequency modulation continuous wave (FMCW) system includes a first memory receiving a clock signal and storing voltage digital values of I FMCW signals, a second memory receiving the clock signal and storing the voltage digital values of the Q FMCW signals, a first digital-to-analog converter (DAC) connected to the first memory and receiving the clock signal for converting the voltage digital values of the I FMCW signal to a first analog voltage, a second digital-to-analog converter (DAC) connected to the second memory and receiving the clock signal for converting the voltage digital values of the Q FMCW signal to a second analog voltage, an I low-pass filter connected to the first DAC smoothing the I FMCW signal and a Q low-pass filter connected to the second DAC smoothing the Q FMCW signal.

摘要翻译： 频率调制连续波（FMCW）系统包括接收时钟信号并存储I FMCW信号的电压数字值的第一存储器，接收时钟信号并存储Q FMCW信号的电压数字值的第二存储器，第一数字 - 模拟转换器（DAC），连接到第一存储器并且接收用于将I FMCW信号的电压数字值转换为第一模拟电压的时钟信号;连接到第二存储器的第二数模转换器（DAC） 并接收用于将Q FMCW信号的电压数字值转换为第二模拟电压的时钟信号，连接到第一DAC的I低通滤波器平滑I FMCW信号和连接到第二DAC的Q低通滤波器 平滑Q FMCW信号。

公开(公告)号：US08351166B2

公开(公告)日：2013-01-08

申请号：US12508665

申请日：2009-07-24

申请人： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

发明人： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

IPC分类号： H01G7/16 ,  G01R31/12

CPC分类号： G01R31/024 ,  G01R31/028

摘要： A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.

摘要翻译： 一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。 每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。 泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。 如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。 可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

公开(公告)号：US20110019321A1

公开(公告)日：2011-01-27

申请号：US12508665

申请日：2009-07-24

申请人： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

发明人： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

IPC分类号： G01R27/26 ,  H02H3/00

CPC分类号： G01R31/024 ,  G01R31/028

摘要： A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.

摘要翻译： 一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。 每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。 泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。 如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。 可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

公开(公告)号：US08860191B2

公开(公告)日：2014-10-14

申请号：US13168512

申请日：2011-06-24

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC分类号： H01L23/66 ,  H01P1/18 ,  H01L23/522

CPC分类号： H01L23/5222 ,  H01L23/5225 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01P1/184 ,  Y10T29/49117 ,  H01L2924/00

摘要： A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.

摘要翻译： 一种传输线路结构，相关设计结构及其相关方法。 公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为 基本上与第二部分相同。

公开(公告)号：US08853693B2

公开(公告)日：2014-10-07

申请号：US13423823

申请日：2012-03-19

申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L21/76898

摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

公开(公告)号：US08566759B2

公开(公告)日：2013-10-22

申请号：US12046750

申请日：2008-03-12

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC分类号： G06F17/50

CPC分类号： G01R1/18 ,  G01R31/2851 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括：围绕和容纳布置在基板上的电路或电路装置的导电结构以及与导电结构相关联的至少一个馈电电容器和一个传输线，并将电源和信号提供给电路或电路装置 分别。 该设计结构还包括围绕设置在基板上的电路或电路装置的屏蔽结构以及布置在屏蔽结构侧的电容器或传输线的至少一个馈电。

公开(公告)号：US08525561B2

公开(公告)日：2013-09-03

申请号：US13275367

申请日：2011-10-18

申请人： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

发明人： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

IPC分类号： H03K21/00

CPC分类号： H03L7/183 ,  H03K23/54

摘要： A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.

摘要翻译： 锁相环（PLL）包括具有反馈分压器的PLL反馈电路。 反馈分压器具有第一动态锁存器，第一逻辑电路和多个串联连接的动态锁存器。 每个串行连接的动态锁存器将附加的数据信号接收并串行连接到后续串行的动态锁存器。 串联中的第二个到最后一个动态锁存器将第四个数据信号输出到该系列中的最后一个动态锁存器。 最后的动态锁存器接收第四数据信号并输出​​第五数据信号。 第一反馈回路从第二到最后动态锁存器接收第四数据信号，并从最后一个动态锁存器接收第五数据信号。 第一反馈环路包括组合第四和第五数据信号的NAND电路，第一反馈环路输出第一反馈信号。

公开(公告)号：US20130093463A1

公开(公告)日：2013-04-18

申请号：US13275369

申请日：2011-10-18

申请人： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

发明人： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

IPC分类号： H03K19/173

CPC分类号： H03K19/1737 ,  H03K19/17744

摘要： A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.

摘要翻译： 动态锁存器具有一对并行通道门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。 第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。 附加的通过门可操作地连接到第一锁存逻辑电路。 一个附加的传递门控制更新的数据信号的通过。 反相器从传递门接收更新的数据信号，并将更新的数据信号反相并输出为输出数据信号。 因此，动态锁存器包括两对输入到该对并行通道门中，并且对接收到的数据信号仅执行四个逻辑运算中的一个。 使用施加到两个输入的信号来执行四个逻辑运算。

公开(公告)号：US08415999B2

公开(公告)日：2013-04-09

申请号：US12845390

申请日：2010-07-28

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhenrong Jin ,  Francis F. Szenher

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhenrong Jin ,  Francis F. Szenher

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/22

摘要： A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.