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    BUILT-IN SELF-TEST METHOD AND STRUCTURE
    2.
    发明申请
    BUILT-IN SELF-TEST METHOD AND STRUCTURE 有权
    内置自检方法和结构

    公开(公告)号：US20130265068A1

    公开(公告)日：2013-10-10

    申请号：US13443450

    申请日：2012-04-10

    申请人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

    发明人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

    IPC分类号： G01R31/3187

    CPC分类号： G01R31/318511 ,  G01R31/2856 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/1206

    摘要： A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.

    摘要翻译： 一种半导体晶片的测试方法及相关结构。 在各种实施例中，一种方法包括：将探针放置在半导体晶片上的第一芯片上; 测试划线自动内置自检（ABIST）为第一芯片寻找故障; 响应于确定第一芯片的ABIST而对半导体晶片上的后续芯片进行随后的划线ABIST的逐步测试不表示故障; 将探针点移动到随后的芯片，并且响应于确定随后芯片的ABIST指示故障，重新测试随后的划线ABIST; 以及响应于确定随后的scribiline的重新测试，测试另一后续划线ABIST用于半导体晶片上的另外的后续芯片，ABIST不指示后续划线ABIST中的故障。

    Built-in self-test method and structure
    3.
    发明授权
    Built-in self-test method and structure 有权
    内置自检方法和结构

    公开(公告)号：US08890557B2

    公开(公告)日：2014-11-18

    申请号：US13443450

    申请日：2012-04-10

    申请人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

    发明人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

    IPC分类号： G01R31/3187

    CPC分类号： G01R31/318511 ,  G01R31/2856 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/1206

    摘要： A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.

    摘要翻译： 一种半导体晶片的测试方法及相关结构。 在各种实施例中，一种方法包括：将探针放置在半导体晶片上的第一芯片上; 测试划线自动内置自检（ABIST）为第一芯片寻找故障; 响应于确定第一芯片的ABIST而对半导体晶片上的后续芯片进行随后的划线ABIST的逐步测试不表示故障; 将探针点移动到随后的芯片，并且响应于确定随后芯片的ABIST指示故障，重新测试随后的划线ABIST; 以及响应于确定随后的scribiline的重新测试，测试另一后续划线ABIST用于半导体晶片上的另外的后续芯片，ABIST不指示后续划线ABIST中的故障。

    CONTACT FORMATION METHOD INCORPORATING A PREVENTATIVE ETCH STEP FOR REDUCING INTERLAYER DIELECTRIC MATERIAL FLAKE DEFECTS
    5.
    发明申请
    CONTACT FORMATION METHOD INCORPORATING A PREVENTATIVE ETCH STEP FOR REDUCING INTERLAYER DIELECTRIC MATERIAL FLAKE DEFECTS 失效
    联合形成方法包含减少中间层介质材料失火的预防蚀刻步骤

    公开(公告)号：US20120064714A1

    公开(公告)日：2012-03-15

    申请号：US12880437

    申请日：2010-09-13

    申请人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    发明人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76877

    摘要： Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

    摘要翻译： 公开了接合形成技术的实施例，其包括预防性蚀刻步骤以减少层间绝缘材料剥落（例如，硼磷硅玻璃（BPSG）剥落），从而减少表面缺陷。 具体地说，可通过化学气相沉积（CVD）沉积的导体层填充通过电介质层延伸到衬底中部和/或中心部分的半导体器件的接触开口。 可以进行导体层的化学机械抛光（CMP）以完成接触结构。 然而，在执行CMP工艺之前（例如，在形成接触开口之前或在填充接触开口之前），可以执行预防蚀刻工艺以从衬底的边缘部分上方去除任何电介质材料。 在CMP之前从衬底的边缘部分上方去除电介质材料减少了由电介质材料剥落引起的表面缺陷的发生。

    Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects
    6.
    发明授权
    Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects 失效
    包含预防性蚀刻步骤的接触形成方法减少层间绝缘材料薄片缺陷

    公开(公告)号：US08691690B2

    公开(公告)日：2014-04-08

    申请号：US12880437

    申请日：2010-09-13

    申请人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    发明人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76877

    摘要： Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

    摘要翻译： 公开了接合形成技术的实施例，其包括预防性蚀刻步骤以减少层间绝缘材料剥落（例如，硼磷硅玻璃（BPSG）剥落），从而减少表面缺陷。 具体地说，可通过化学气相沉积（CVD）沉积的导体层填充通过电介质层延伸到衬底中部和/或中心部分的半导体器件的接触开口。 可以进行导体层的化学机械抛光（CMP）以完成接触结构。 然而，在执行CMP工艺之前（例如，在形成接触开口之前或在填充接触开口之前），可以执行预防蚀刻工艺以从衬底的边缘部分上方去除任何电介质材料。 在CMP之前从衬底的边缘部分上方去除电介质材料减少了由电介质材料剥落引起的表面缺陷的发生。