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    Asynchronous low latency data recovery apparatus and method
    3.
    发明授权
    Asynchronous low latency data recovery apparatus and method 失效
    异步低延迟数据恢复装置和方法

    公开(公告)号：US5610953A

    公开(公告)日：1997-03-11

    申请号：US407928

    申请日：1995-03-21

    申请人： Robert Betts ,  Howard T. Olnowich

    发明人： Robert Betts ,  Howard T. Olnowich

    IPC分类号： G06F1/12 ,  G06F13/00 ,  H03M9/00 ,  H04L7/033 ,  H04L7/04 ,  H04L12/18 ,  H04L12/56 ,  H04Q11/00 ,  H04L7/00

    CPC分类号： H03M9/00 ,  H04L49/256 ,  H04L49/3081 ,  H04L7/0338 ,  H04L7/044 ,  H04L12/1881 ,  H04L2012/5627 ,  H04Q11/0066

    摘要： A receiver device is provided with a low latency recovery apparatus for recovering serially transmitted digital data. The receiver device operates asynchronously in respect to a transmitting device. The low latency recovery apparatus synchronizes the receiver device in one clock time to support throughput of high speed transmission messages received from interconnection networks or interface cables. A metastability proof latch is provided. A synchronization method provides individual alignment for each incoming message. There is instantaneous response to back-to-back messages from different sources. Synchronization is accomplished in the receiving device by implementing a clocking system capable of generating N phase-shifted clocks all operating at the same frequency as the incoming data. The N clocks are shifted an approximately equal amount in relation to each other. The data recovery apparatus selects the one of N clocks which is best in synchronization with the incoming serial data and then to receive the message correctly. The apparatus has a two wire interface for serial data and a bracketing control signal. Serial data is synchronized first to the selected clock and then to a local clock. The bracketing control signals when each message recovery is complete and triggers the start of another message recovery in as little as one clock time.

    摘要翻译： 接收机设备具有用于恢复串行传输的数字数据的低延迟恢复装置。 接收机设备相对于发射设备异步地操作。 低延迟恢复装置在一个时钟时间内同步接收机设备，以支持从互连网络或接口电缆接收的高速传输消息的吞吐量。 提供了一种亚稳定性闩锁。 同步方法为每个传入消息提供单独的对齐。 对来自不同来源的背对背消息有即时响应。 通过实现能够产生N个相移时钟的时钟系统，在接收设备中实现同步，该时钟系统以与输入数据相同的频率工作。 N个时钟相对于彼此移动大致相等的量。 数据恢复装置选择与输入串行数据同步最佳的N个时钟之一，然后正确地接收该消息。 该装置具有用于串行数据和包围控制信号的双线接口。 串行数据首先与选定的时钟同步到本地时钟。 每个消息恢复完成时，包围控制信号，并在短短一个时钟内触发另一个消息恢复的开始。

    Priority interrupt switching apparatus for real time systems
    4.
    发明授权
    Priority interrupt switching apparatus for real time systems 失效
    用于实时系统的优先中断切换装置

    公开(公告)号：US5404537A

    公开(公告)日：1995-04-04

    申请号：US946986

    申请日：1992-09-17

    申请人： Howard T. Olnowich ,  David B. Kirk

    发明人： Howard T. Olnowich ,  David B. Kirk

    IPC分类号： G06F15/173 ,  G06F9/46 ,  G06F15/16

    CPC分类号： G06F15/17375

    摘要： A method and apparatus for implementing intelligent priority functions at individual switching apparatus devices which comprise switching networks. The intelligent switching functions are capable of operating in real time systems with high efficiency. The switching apparatus has the capability at each stage of the network to make and/or break connections on a priority basis. If a connection is requested at a switch stage and the connection is being used by a lower priority device, the low priority connection is interrupted (broken) and the requested higher priority connection is established. After the high priority connection has completed its usage of the connection, the high priority connection is broken and the lower priority connection is re-established.

    摘要翻译： 一种用于在包括交换网络的各个交换设备设备处实现智能优先级功能的方法和装置。 智能切换功能能够以高效率在实时系统中运行。 交换设备在网络的每个阶段具有在优先级上进行和/或断开连接的能力。 如果在交换阶段请求了连接，并且较低优先级的设备正在使用该连接，则低优先级连接将被中断（断开），并建立所请求的较高优先级连接。 高优先级连接完成连接使用后，高优先级连接断开，优先级较低的连接重新建立。

    Protocol-to-protocol translator for interfacing disparate serial network nodes to a common parallel switching network
    5.
    发明授权
    Protocol-to-protocol translator for interfacing disparate serial network nodes to a common parallel switching network 失效
    协议到协议转换器，用于将不同的串行网络节点连接到公共并行交换网络

    公开(公告)号：US5535373A

    公开(公告)日：1996-07-09

    申请号：US390893

    申请日：1995-02-15

    申请人： Howard T. Olnowich

    发明人： Howard T. Olnowich

    IPC分类号： H04Q3/52 ,  G06F15/173 ,  H04L1/00 ,  H04L7/033 ,  H04L12/18 ,  H04L12/56 ,  H04L29/04 ,  H04L29/06 ,  H04Q11/00 ,  G06F3/00

    CPC分类号： H04L1/0057 ,  G06F15/17375 ,  H04L29/06 ,  H04L49/1523 ,  H04L7/0338 ,  H04L12/1881 ,  H04L49/101 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/357 ,  H04L69/08 ,  H04L69/18 ,  H04Q11/0066

    摘要： A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to a parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations. Further flexibility is provided which permits the switching adapter to be personalized to support any one of a number of standard and proprietary serial protocols. A personalization PROM specifies the particular serial protocol that each individual adapter is to support. The parallel switching network becomes a flexible media that interconnects and allows different serial protocols to communicate with each other; i.e., any number of different serial protocols can interface with the same parallel switch network. This allows every node of the parallel system to send and receive messages using its own native protocol. However, a node is not restricted to communicating only with others nodes using the same protocol, but is can communicate with any of the other nodes regardless of the serial protocol they use.

    摘要翻译： 通用网络设备包括用于通过交换网络在多个节点之间执行并行或串行通信的串行线路交换设备。 一个方面包括使用光或电传输介质来适应与并行交换机接口的标准和专有串行接口。 转换的串行数据通过并行交换网络路由到所选择的目的地，其中它被接收并转换回串行光或电接口/协议。 因此，开关适配器和ALLNODE并行交换网络的组合使得将串行消息数据切换并路由到各种目的地是可行的。 提供了进一步的灵活性，其允许将开关适配器个性化以支持多种标准和专有串行协议中的任何一种。 个性化PROM指定每个单独的适配器要支持的特定串行协议。 并行交换网络成为互连并允许不同串行协议相互通信的灵活媒体; 即任何数量的不同的串行协议都可以与同一个并行交换网络相连接。 这允许并行系统的每个节点使用自己的本地协议发送和接收消息。 然而，节点不限于使用相同协议与其他节点进行通信，而是可以与任何其他节点进行通信，而不管其使用的串行协议如何。

    Dual priority switching apparatus for simplex networks
    6.
    发明授权
    Dual priority switching apparatus for simplex networks 失效
    用于单工网络的双重优先切换装置

    公开(公告)号：US5444705A

    公开(公告)日：1995-08-22

    申请号：US800652

    申请日：1991-11-27

    申请人： Howard T. Olnowich ,  Thomas N. Barker ,  Peter M. Kogge ,  Gilbert C. Vandling, III

    发明人： Howard T. Olnowich ,  Thomas N. Barker ,  Peter M. Kogge ,  Gilbert C. Vandling, III

    IPC分类号： G06F11/26 ,  G06F13/364 ,  G06F13/40 ,  G06F15/173 ,  H03M9/00 ,  H04L1/00 ,  H04L7/033 ,  H04L7/04 ,  H04L12/18 ,  H04L12/56 ,  H04Q11/00 ,  H04Q11/04 ,  H04J3/02

    CPC分类号： H04L1/0057 ,  G06F13/364 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17393 ,  H03M9/00 ,  H04L49/205 ,  H04L7/0338 ,  H04L7/044 ,  H04Q11/0478 ,  G06F11/261 ,  H04L49/101 ,  H04L49/1515 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/40 ,  H04L49/55 ,  H04Q11/0066

    摘要： A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses as asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can be used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two. The switch has a single physical network path element over which either a low priority or high priority path can be established.

    摘要翻译： 通过多级交换网络将高优先级路径添加到正常的低优先级路径。 高优先级路径以最快的速度建立，因为高优先级命令存储在所涉及的切换阶段，并且一旦输出端口变得可用就在优先级基础上进行。 另外，在建立连接时立即建立连接的节点，使得它可以在尽可能早的时刻进行肯定的反馈。 高优先级路径能够处理多个高优先级待处理请求，并且使用实现旋转优先级的快照寄存器来解决高优先权争用，使得没有一个请求设备可以被锁定或经历数据不足。 具有与输出端口连接的输入端口连接的双重优先级交换设备使用作为异步方式来在低优先级和无阻塞条件下解决争用，并且自动切换到解决争用的优先级驱动的同步装置。 该协议需要几条并行数据线加上四条控制线，使得交换设备可用于具有多个节点的网络，每个节点具有多个输入和输出端口，每个输出端口具有多路复用器控制电路，用于连接任何 的I输入到任何Z输出，其中I和Z可以采用大于或等于2的任何唯一值。 交换机具有单个物理网络路径元素，通过该单个物理网络路径元素可以建立低优先级或高优先级路径。

    Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction
    8.
    发明授权
    Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction 失效
    在执行微分支指令期间避免流水线处理器中的过度延迟的方法和装置

    公开(公告)号：US4701842A

    公开(公告)日：1987-10-20

    申请号：US784073

    申请日：1985-10-04

    申请人： Howard T. Olnowich

    发明人： Howard T. Olnowich

    IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/28

    CPC分类号： G06F9/28 ,  G06F9/265

    摘要： In a pipelined instruction execution system including a microstore for storing sequences of microinstruction addresses associated with each macroinstruction, a nanostore for randomly storing unique microinstructions, and an execution unit for executing the microinstructions, a no-op/prefetch apparatus, according to the present invention, prevents a microinstruction address, stored in the microstore, from accessing the nanostore and forces a no-op address into the nanostore when the execution unit executes a conditional microbranch instruction. A no-op microinstruction, corresponding to the no-op address, is retrieved from the nanostore and is executed in the execution unit. During the execution of the no-op microinstruction in the execution unit, the no-op/prefetch apparatus permits either the next sequential microinstruction address following the conditional microbranch instruction to access the nanostore or another non-sequential microinstruction address to access the nanostore, the selection of the next sequential microinstruction address or said another non-sequential microinstruction depending upon the outcome of the execution of the conditional microbranch instruction by the execution unit. As a result, when the microstore and the nanostore are utilized, only one cycle of delay, for resolution of the pipeline, will be encountered following the execution of the conditional branch microinstruction by the execution unit. Furthermore, additional real estate is available on the integrated circuit chip on which the instruction execution system is disposed.

    摘要翻译： 在包括用于存储与每个宏指令相关联的微指令地址序列的微存储器的流水线指令执行系统中，用于随机存储唯一微指令的纳斯塔，以及用于执行微指令的执行单元，根据本发明的无操作/预取装置 当执行单元执行条件微分支指令时，防止存储在微型存储器中的微指令地址访问纳斯塔，并迫使无操作地址进入纳斯塔。 对应于无操作地址的无操作微指令从纳索尔检索并在执行单元中执行。 在执行单元中的无操作微指令执行期间，无操作/预取装置允许遵循条件微分支指令的下一个顺序微指令地址访问纳索波斯或另一个非顺序微指令地址以访问纳斯波特， 取决于执行单元执行条件微分支指令的结果，选择下一个顺序微指令地址或所述另一非连续微指令。 结果，当使用微型存储器和纳斯塔尔时，在由执行单元执行条件分支微指令之后将仅遇到用于解析流水线的一个延迟周期。 此外，在其上设置有指令执行系统的集成电路芯片上提供额外的房地产。

    Apparatus for programming the speed at which an expansion card generates ready signals to insure compatibility with the speed of an attached bus
    10.
    发明授权
    Apparatus for programming the speed at which an expansion card generates ready signals to insure compatibility with the speed of an attached bus 失效
    用于对扩展卡产生就绪信号的速度进行编程的装置，以确保与附接总线的速度的兼容性

    公开(公告)号：US5465333A

    公开(公告)日：1995-11-07

    申请号：US389606

    申请日：1995-02-15

    申请人： Howard T. Olnowich

    发明人： Howard T. Olnowich

    IPC分类号： G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/4217 ,  G06F13/423

    摘要： An apparatus is disclosed for processing information including a bus, a controller circuit, the controller circuit being configured to control transfer of information over the bus, and a slave circuit. The slave circuit includes a slave timing circuit which variably generates a ready signal indicating when the slave can accept data to allow the slave circuit to function in computer systems having different bus speeds. The controller circuit and the slave circuit exchange information via the bus at a speed controlled by the ready signal.

    摘要翻译： 公开了一种用于处理信息的装置，包括总线，控制器电路，控制器电路被配置为控制通过总线的信息传输和从电路。 从电路包括从时序电路，其可变地产生就绪信号，指示从机可以接受数据以允许从电路在具有不同总线速度的计算机系统中起作用的就绪信号。 控制器电路和从机通过总线以由就绪信号控制的速度交换信息。