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公开(公告)号：US5819286A
公开(公告)日：1998-10-06
申请号：US570212
申请日：1995-12-11
IPC分类号： G06F17/30
CPC分类号： G06K9/00744 , G06F17/30831 , G06F17/30834 , G06K9/468 , Y10S707/99931 , Y10S707/99945
摘要： A video indexing and query execution system includes a processor which indexes video clips by: (a) identifying each symbol of one or more graphical icons in each frame of each video clip, (b) determining the horizontal, vertical and temporal coordinates of each symbol of the identified graphical icons, and (c) constructing a database for each identified symbol of the graphical icons. The processor converts a video query from graphical form to string form by: (a) receiving a video query specifying the vertical, horizontal and temporal coordinates of a graphical icon to be matched in at least one frame to be retrieved, and (b) constructing a normal 3-D string from the video query indicating the distance between each symbol of each icon in the video query in each direction. The processor also executes a video query on a video database by: (a) identifying only those video clips of the database whose signatures contain the signature of the executed video query, (b) for each of the identified video clips: (b1) constructing a 1-D list for each of the horizontal, vertical and temporal directions, comprising a plurality of sets of symbols of icons contained in video query, each set containing a permutation of symbols of the icons which satisfy the video query in the respective direction of the 1-D list, and (b2) forming the intersection of the three 1-D lists, and (c) identifying the portions of the video clips, indicated by a corresponding set contained in an intersection set of at least one of the identified video clips, as satisfying the video query.
摘要翻译： 视频索引和查询执行系统包括：处理器，其通过以下步骤对视频剪辑进行索引：（a）识别每个视频剪辑的每个帧中的一个或多个图形图标的每个符号，（b）确定每个符号的水平，垂直和时间坐标 的识别图形图标，以及（c）为图形图标的每个识别的符号构建数据库。 处理器通过以下方式将视频查询转换成图形形式到字符串形式：（a）接收指定要在要检索的至少一个帧中匹配的图形图标的垂直，水平和时间坐标的视频查询，以及（b）构建 来自视频查询的正常3-D字符串，指示每个方向上视频查询中每个图标的每个符号之间的距离。 处理器还通过以下方式对视频数据库执行视频查询：（a）仅识别其签名包含执行的视频查询的签名的数据库的视频剪辑，（b）针对每个所识别的视频剪辑：（b1）构造 用于水平，垂直和时间方向中的每一个的1-D列表，包括视频查询中包含的图标的多组符号集合，每个集合包含满足在相应方向上的视频查询的图标的符号排列 所述1-D列表和（b2）形成三个1-D列表的交集，以及（c）识别由包含在所识别的至少一个的交集中的相应集合所指示的视频剪辑的部分 视频剪辑，满足视频查询。
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公开(公告)号：US06916702B2
公开(公告)日：2005-07-12
申请号：US10951763
申请日：2004-09-29
申请人： Shih-Ming Chen , Hsiao-Ying Yang
发明人： Shih-Ming Chen , Hsiao-Ying Yang
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531
摘要： A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.
摘要翻译： 嵌入式存储器件的栅极处理和栅极处理。 半导体硅衬底具有存储单元区域和逻辑电路区域。 在半导体硅衬底上形成第一电介质层，然后形成覆盖在存储单元区域的第一介电层上的栅极结构。 接下来，形成覆盖第一电介质层和栅极结构的顶部和侧壁的保护层。 接下来，形成覆盖在栅极结构的侧壁上的保护层的绝缘间隔物。 接下来，执行预清洁处理以去除覆盖在逻辑电路区域上的保护层和第一介电层。 接下来，形成覆盖逻辑电路区域的第二介电层，然后形成覆盖逻辑电路区域的第二介电层的栅极层。
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公开(公告)号：US20110062500A1
公开(公告)日：2011-03-17
申请号：US12953347
申请日：2010-11-23
申请人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang , Ya-Sheng Liu
发明人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang , Ya-Sheng Liu
IPC分类号： H01L29/80
CPC分类号： H01L29/7836 , H01L29/0653
摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。
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公开(公告)号：US20090236681A1
公开(公告)日：2009-09-24
申请号：US12177779
申请日：2008-07-22
CPC分类号： H01L21/823481 , H01L21/823412 , H01L21/823493 , H01L21/823807 , H01L21/823878 , H01L21/823892
摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.
摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。
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公开(公告)号：US20050042811A1
公开(公告)日：2005-02-24
申请号：US10951763
申请日：2004-09-29
申请人： Shih-Ming Chen , Hsiao-Ying Yang
发明人： Shih-Ming Chen , Hsiao-Ying Yang
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531
摘要： A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.
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公开(公告)号：US20120056295A1
公开(公告)日：2012-03-08
申请号：US13294945
申请日：2011-11-11
IPC分类号： H01L27/06
CPC分类号： H01L21/823481 , H01L21/823412 , H01L21/823493 , H01L21/823807 , H01L21/823878 , H01L21/823892
摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.
摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。
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公开(公告)号：US20090236665A1
公开(公告)日：2009-09-24
申请号：US12177766
申请日：2008-07-22
申请人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang , Ya-Sheng Liu
发明人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang , Ya-Sheng Liu
IPC分类号： H01L21/336 , H01L29/78 , H01L21/027
CPC分类号： H01L29/7836 , H01L29/0653
摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。
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8.发明授权公开(公告)号：US06482702B1
公开(公告)日：2002-11-19
申请号：US10093486
申请日：2002-03-11
申请人： Chi-Hua Yu , Hsiao-Ying Yang
发明人： Chi-Hua Yu , Hsiao-Ying Yang
IPC分类号： H01L28236
CPC分类号： H01L27/11253 , H01L23/544 , H01L27/112 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： A method of forming and recognizing an identification mark for read-only memory. First, a first patterned resist layer is formed on a semiconductor substrate having an insulating region and a device region thereon by a code mask having code and identification mark patterns, and the identification mark pattern is over the insulating region. Next, ion implantation is performed to code in the device region. Thereafter, a second patterned resist layer is formed on the first patterned resist layer by a common mask to expose the entire identification mark pattern of the first patterned resist layer only. The identification mark pattern is then transferred to the insulating region by dry etching. Finally, the substrate having a clear identification mark is placed in an optical microscope for identification by an operator.
摘要翻译： 形成和识别只读存储器的识别标记的方法。 首先，通过具有代码和识别标记图案的代码掩模，在其上具有绝缘区域和器件区域的半导体衬底上形成第一图案化抗蚀剂层，并且识别标记图案在绝缘区域之上。 接下来，执行离子注入以在器件区域中编码。 此后，通过共用掩模在第一图案化抗蚀剂层上形成第二图案化抗蚀剂层，以仅暴露第一图案化抗蚀剂层的整个识别标记图案。 然后通过干蚀刻将识别标记图案转移到绝缘区域。 最后，将具有清晰识别标记的基板放置在光学显微镜中以供操作员识别。
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9.发明授权Method for fabricating semiconductor device with increased breakdown voltage 有权制造具有增加的击穿电压的半导体器件的方法公开(公告)号：US08080455B2
公开(公告)日：2011-12-20
申请号：US12177779
申请日：2008-07-22
IPC分类号： H01L21/8238
CPC分类号： H01L21/823481 , H01L21/823412 , H01L21/823493 , H01L21/823807 , H01L21/823878 , H01L21/823892
摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.
摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。
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公开(公告)号：US08063439B2
公开(公告)日：2011-11-22
申请号：US12953347
申请日：2010-11-23
申请人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang , Ya-Sheng Liu
发明人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang , Ya-Sheng Liu
IPC分类号： H01L29/80
CPC分类号： H01L29/7836 , H01L29/0653
摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
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