公开(公告)号：US06916702B2

公开(公告)日：2005-07-12

申请号：US10951763

申请日：2004-09-29

申请人： Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11531

摘要： A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.

摘要翻译： 嵌入式存储器件的栅极处理和栅极处理。 半导体硅衬底具有存储单元区域和逻辑电路区域。 在半导体硅衬底上形成第一电介质层，然后形成覆盖在存储单元区域的第一介电层上的栅极结构。 接下来，形成覆盖第一电介质层和栅极结构的顶部和侧壁的保护层。 接下来，形成覆盖在栅极结构的侧壁上的保护层的绝缘间隔物。 接下来，执行预清洁处理以去除覆盖在逻辑电路区域上的保护层和第一介电层。 接下来，形成覆盖逻辑电路区域的第二介电层，然后形成覆盖逻辑电路区域的第二介电层的栅极层。

公开(公告)号：US20120056295A1

公开(公告)日：2012-03-08

申请号：US13294945

申请日：2011-11-11

申请人： CHIH-PING LIN ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： CHIH-PING LIN ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L27/06

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US20090236665A1

公开(公告)日：2009-09-24

申请号：US12177766

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/027

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。

公开(公告)号：US20110062500A1

公开(公告)日：2011-03-17

申请号：US12953347

申请日：2010-11-23

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L29/80

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。

公开(公告)号：US20090236681A1

公开(公告)日：2009-09-24

申请号：US12177779

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US20050042811A1

公开(公告)日：2005-02-24

申请号：US10951763

申请日：2004-09-29

申请人： Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11531

摘要： A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.

公开(公告)号：US08080455B2

公开(公告)日：2011-12-20

申请号：US12177779

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US08063439B2

公开(公告)日：2011-11-22

申请号：US12953347

申请日：2010-11-23

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L29/80

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

公开(公告)号：US07863147B2

公开(公告)日：2011-01-04

申请号：US12177766

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L21/00

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。

公开(公告)号：US20100181639A1

公开(公告)日：2010-07-22

申请号：US12356036

申请日：2009-01-19

申请人： Wei-Tsung Huang ,  Pi-Kuang Chuang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Wei-Tsung Huang ,  Pi-Kuang Chuang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L23/58 ,  H01L21/76

CPC分类号： H01L21/763 ,  H01L21/823481 ,  H01L21/823878

摘要： A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices.

摘要翻译： 提供半导体器件。 半导体器件包括设置在半导体衬底上的外延层，设置在外延层上的多个电子器件和设置在电气器件之间的沟槽隔离结构。 沟槽隔离结构包括在外延层和半导体衬底中的沟槽，沟槽的侧壁和底部上的氧化物衬垫以及填充在沟槽中的掺杂多晶硅层。 此外，零偏压可以施加到掺杂多晶硅层。 沟槽隔离结构可以用于隔离具有不同操作电压的电子器件或高压器件。