公开(公告)号：US20100279436A1

公开(公告)日：2010-11-04

申请号：US12433525

申请日：2009-04-30

申请人： Hsueh-Hung Fu ,  Tsung-Fu Hsieh ,  Chih-Wei Chang ,  Shih-Chang Chen

发明人： Hsueh-Hung Fu ,  Tsung-Fu Hsieh ,  Chih-Wei Chang ,  Shih-Chang Chen

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method for manufacturing integrated circuit devices including an electron beam inspection. The method includes forming a silicide region on a substrate. In an embodiment, the silicide region is formed to provide contact to a device feature such as a source or drain region. An electron beam scan is then performed on the substrate. The electron beam scan includes a first scan and a second scan. The first scan includes a lower landing energy than the second scan. In an embodiment, the first scan provides a dark silicide image analysis and a bright image analysis. In an embodiment, the second scan provides a dark silicide image analysis. The method continues to form a conductive plug after performing the electron beam scan.

摘要翻译： 本公开提供了一种用于制造包括电子束检查的集成电路器件的方法。 该方法包括在衬底上形成硅化物区域。 在一个实施例中，形成硅化物区域以提供与诸如源极或漏极区域的器件特征的接触。 然后在衬底上进行电子束扫描。 电子束扫描包括第一扫描和第二扫描。 第一扫描包括比第二次扫描更低的着陆能量。 在一个实施例中，第一扫描提供深色硅化物图像分析和明亮图像分析。 在一个实施例中，第二扫描提供黑暗硅化物图像分析。 该方法在进行电子束扫描之后继续形成导电塞。

公开(公告)号：US20080199978A1

公开(公告)日：2008-08-21

申请号：US11707662

申请日：2007-02-16

申请人： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

发明人： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

IPC分类号： G01R31/26

CPC分类号： G01R31/2831 ,  H01L22/12

摘要： A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.

摘要翻译： 在晶片上形成当前顶层之后测试晶片的方法。 在形成当前顶层之后，为晶片收集应力数据。 应力数据来源于晶片曲率的变化。 应力数据包括：在x方向上的应力x x和在晶片上的一组有限区域的每个区域的ay方向上的应力yy，应力xx和应力yy都源自晶片曲率变化 - x x在x方向上对于有限区域集合中的每个区域以及从y方向的晶片曲率变化yy到该有限区域集合中的每个区域; 并且应力xy从晶片曲率变化xy得到，其中晶片曲率变化xy是在该有限区域的每个区域的x-y平面中的晶片扭转的变化。 应力梯度矢量（和/或其范数）被计算并用于评估调查单个或多个累积层。

公开(公告)号：US07805258B2

公开(公告)日：2010-09-28

申请号：US11707662

申请日：2007-02-16

申请人： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

发明人： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： G01R31/2831 ,  H01L22/12

摘要： A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.

摘要翻译： 在晶片上形成当前顶层之后测试晶片的方法。 在形成当前顶层之后，为晶片收集应力数据。 应力数据来源于晶片曲率的变化。 应力数据包括：在x方向上的应力x x和在晶片上的一组有限区域的每个区域的ay方向上的应力yy，应力xx和应力yy都源自晶片曲率变化 - x x在x方向上对于有限区域集合中的每个区域以及从y方向的晶片曲率变化yy到该有限区域集合中的每个区域; 并且应力xy从晶片曲率变化xy得到，其中晶片曲率变化xy是在该有限区域的每个区域的x-y平面中的晶片扭转的变化。 应力梯度矢量（和/或其范数）被计算并用于评估调查单个或多个累积层。

公开(公告)号：US20150173225A1

公开(公告)日：2015-06-18

申请号：US14108339

申请日：2013-12-17

申请人： Cheng-Chao Peng ,  Ke-Sheng Huang ,  Yung-Chih Kuo ,  Chih-Wei Chang ,  Wen-Hua Yu ,  Yu-Yi Wu ,  Yu-Yuan Lin

发明人： Cheng-Chao Peng ,  Ke-Sheng Huang ,  Yung-Chih Kuo ,  Chih-Wei Chang ,  Wen-Hua Yu ,  Yu-Yi Wu ,  Yu-Yuan Lin

IPC分类号： H05K5/03 ,  H05K5/00 ,  H05K13/00 ,  H05K5/02

CPC分类号： G06F1/16 ,  G02F1/133308 ,  G02F2001/133317 ,  G02F2001/133322 ,  G02F2001/133325 ,  G06F1/1616 ,  G06F1/1637 ,  Y10T29/49826

摘要： A display device comprises a cover and a display module. The cover includes a bottom plate and at least one cover limit element. The cover limit element projects inwardly from an inner surface of the bottom of the cover. A space is formed between the bottom plate and the cover limit element. The display module includes a frame with at least one frame limit element disposed at an end of the frame and projecting at a position between the cover limit element and the bottom plate. The frame limit element is configured to be disposed in the space and between the cover limit element and the bottom plate to retain the display module with the cover.

摘要翻译： 显示装置包括盖和显示模块。 盖包括底板和至少一个盖限制元件。 盖限制元件从盖的底部的内表面向内突出。 在底板和盖限位元件之间形成空间。 显示模块包括框架，框架具有至少一个框架限制元件，该框架限定元件设置在框架的端部处，并且在覆盖限制元件和底板之间的位置处突出。 框架限制元件被配置为设置在空间中并且在盖限制元件和底板之间以将盖子保持在显示模块上。

公开(公告)号：US08541697B2

公开(公告)日：2013-09-24

申请号：US13031710

申请日：2011-02-22

申请人： Chih-Wei Chang

发明人： Chih-Wei Chang

IPC分类号： H05K5/06 ,  H04M1/00

CPC分类号： H04M1/0266

摘要： A dustproof structure is used in an electronic device, which includes a housing and a display panel. The dustproof structure includes a dustproof section and a first adhesive section. The dustproof section is located and received in the housing. The first adhesive section is fixed on the one side of the dustproof section, and the display panel is fixed on the dustproof structure by the first adhesive section and is assembled to the housing. The dustproof structure fills gaps between the housing and the display panel.

摘要翻译： 在电子设备中使用防尘结构，其包括壳体和显示面板。 防尘结构包括防尘部和第一粘合部。 防尘部分定位并接收在外壳中。 第一粘合部固定在防尘部的一侧，显示面板通过第一粘合部固定在防尘结构上，并组装到壳体。 防尘结构填充外壳和显示面板之间的间隙。

公开(公告)号：US20120092593A1

公开(公告)日：2012-04-19

申请号：US12970967

申请日：2010-12-17

申请人： Chih-Wei Chang ,  Po-Chun Hsu ,  Kun-Hung Hsieh

发明人： Chih-Wei Chang ,  Po-Chun Hsu ,  Kun-Hung Hsieh

IPC分类号： G02F1/1335 ,  H05K5/02 ,  F21V7/22

CPC分类号： G02B6/0085 ,  G02B6/0088 ,  G02B6/009

摘要： A frame formed by cutting and bending a plate base is provided. The maximum thickness of the frame is T, the thickness of the plate base is t, and 1.5t≦T≦2.5t. The frame includes a first plate element, a second plate element, and a bending portion. The second plate element is directly contacted to the first plate element, and the first plate element is substantially parallel to the second plate element. The bending portion is connected between the first plate element and the second plate element. A backlight module using the above-mentioned frame and a liquid crystal display (LCD) module using the backlight module are also provided.

摘要翻译： 提供了通过切割和弯曲板底座形成的框架。 框架的最大厚度为T，板底的厚度为t，1.5t＆nlE; T＆nlE; 2.5t。 框架包括第一板元件，第二板元件和弯曲部分。 第二板元件直接接触第一板元件，第一板元件基本上平行于第二板元件。 弯曲部分连接在第一板元件和第二板元件之间。 还提供了使用上述框架的背光模块和使用背光模块的液晶显示器（LCD）模块。

公开(公告)号：US20110090141A1

公开(公告)日：2011-04-21

申请号：US12684128

申请日：2010-01-08

申请人： Super Liao ,  Po-Chun Hsu ,  Chih-Wei Chang

发明人： Super Liao ,  Po-Chun Hsu ,  Chih-Wei Chang

IPC分类号： G09G3/36 ,  G02F1/13357

CPC分类号： G09G3/3426 ,  G02B6/0046 ,  G02B6/005 ,  G02B6/0068 ,  G02B6/008 ,  G02B6/0083 ,  G09G2300/0426 ,  G09G2320/0233

摘要： A backlight module including a light guide plate, light source sets, and controlling circuits is provided. The light guide plate has a plurality of regions, and each region of the light guide plate has a light incident surface correspondingly. Each light source set is disposed at the light incident surface of one of the regions of the light guide plate, and each light source set has at least one middle light source and at least one edge light source. The middle light source is disposed in a middle region of the light source set and the edge light source is disposed at an edge of the light source set. Each controlling circuit is electrically connected to the middle light source of one of the light source sets, and the edge light source of each light source set is electrically connected to the controlling circuit of the adjacent light source set.

摘要翻译： 提供了包括导光板，光源组和控制电路的背光模块。 导光板具有多个区域，导光板的各个区域相应地具有光入射面。 每个光源组设置在导光板的一个区域的光入射表面处，并且每个光源组具有至少一个中间光源和至少一个边缘光源。 中间光源设置在光源组的中间区域中，并且边缘光源设置在光源组的边缘。 每个控制电路电连接到一个光源组的中间光源，并且每个光源组的边缘光源电连接到相邻光源组的控制电路。

公开(公告)号：US07405151B2

公开(公告)日：2008-07-29

申请号：US11420900

申请日：2006-05-30

申请人： Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/31625 ,  H01L23/482 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is described. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.

摘要翻译： 对半导体装置的形成方法进行说明。 在第一电介质层中形成开口，暴露晶体管的有源区，并且在开口中以厚度小于等于一致地形成原子层沉积（ALD）TaN势垒。 在原子层沉积（ALD）TaN势垒上形成铜层以填充开口。

公开(公告)号：US20080121929A1

公开(公告)日：2008-05-29

申请号：US11523683

申请日：2006-09-19

申请人： Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/7848 ,  Y10S438/933

摘要： A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer, and a silicide layer on the second silicon-containing layer. The element in the second silicon-containing layer has a second atomic percentage of the element to the element and silicon, wherein the second atomic percentage is substantially lower than the first atomic percentage.

公开(公告)号：US20070284703A1

公开(公告)日：2007-12-13

申请号：US11447989

申请日：2006-06-07

申请人： Kuo-Liang Wu ,  Kuo-Shu Iu ,  Chih-Wei Chang

发明人： Kuo-Liang Wu ,  Kuo-Shu Iu ,  Chih-Wei Chang

IPC分类号： H01L23/495

CPC分类号： H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L2224/37011 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/84385 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/37099

摘要： A semiconductor package structure includes a substrate, a chip module, a lead frame, and a bridging element. The chip module is electrically connected to the substrate. The lead frame is disposed beside one side of the substrate, and the lead frame has a projecting block unit. The bridging element has one side electrically connected with the chip module, and a first positioning unit formed on the other side thereof for electrically retaining with the projecting block unit. Moreover, the semiconductor package structure of the present invention is applied to a design of multi-chip package, and ensures that a bridging element is connected with a chip via the bridging element being retained by a lead frame. In addition, the junction between the bridging element and the lead frame do not cause displacement between the lead frame and the bridging element during the packaging process.

摘要翻译： 半导体封装结构包括衬底，芯片模块，引线框架和桥接元件。 芯片模块电连接到基板。 引线框架设置在基板的一侧旁边，引线框架具有突出块单元。 桥接元件具有与芯片模块电连接的一侧，以及形成在其另一侧上用于与突出块单元电保持的第一定位单元。 此外，本发明的半导体封装结构应用于多芯片封装的设计，并且确保桥接元件通过由引线框架保持的桥接元件与芯片连接。 此外，在包装过程中，桥接元件和引线框架之间的连接点不会引起引线框架和桥接元件之间的位移。