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公开(公告)号：US20170194282A1
公开(公告)日：2017-07-06
申请号：US15467484
申请日：2017-03-23
发明人： An Huang , Yanhai Lin , Wei Liu
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/49 , H01L23/488 , H01L23/66 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L2223/6611 , H01L2224/45124 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48137 , H01L2224/48195 , H01L2224/49052 , H01L2224/4909 , H01L2224/4912 , H01L2224/49175 , H01L2225/06506 , H01L2924/00014 , H01L2224/05599 , H01L2924/20657 , H01L2224/45099
摘要： The application provides an apparatus, including a first section, a second section, and a first bonding wire group, where the first bonding wire group includes at least three first bonding wire units. The first bonding wire unit includes at least one arc-shaped bonding wire, one end and the other end of the first bonding wire unit are electrically connected to electrodes of the first section and the second section, respectively, where arc heights of first bonding wire units located at two sides of the first bonding wire group are higher than an arc height of a first bonding wire unit at another position, and an arc height of a first bonding wire unit located in a central area of the first bonding wire group is lower than an arc height of a first bonding wire unit at another position.
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公开(公告)号：US10347596B2
公开(公告)日：2019-07-09
申请号：US15467484
申请日：2017-03-23
发明人： An Huang , Yanhai Lin , Wei Liu
IPC分类号： H01L23/66 , H01L23/00 , H01L23/488 , H01L25/065
摘要： The application provides an apparatus, including a first section, a second section, and a first bonding wire group, where the first bonding wire group includes at least three first bonding wire units. The first bonding wire unit includes at least one arc-shaped bonding wire, one end and the other end of the first bonding wire unit are electrically connected to electrodes of the first section and the second section, respectively, where arc heights of first bonding wire units located at two sides of the first bonding wire group are higher than an arc height of a first bonding wire unit at another position, and an arc height of a first bonding wire unit located in a central area of the first bonding wire group is lower than an arc height of a first bonding wire unit at another position.
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公开(公告)号：US09866181B2
公开(公告)日：2018-01-09
申请号：US15270954
申请日：2016-09-20
发明人： Xiaomin Zhang , An Huang , Liuyan Jiao
CPC分类号： H03F1/3241 , H03F1/3205 , H03F3/193 , H03F3/195 , H03F3/245 , H03F2200/18 , H03F2200/222 , H03F2200/387 , H03F2200/451
摘要： Embodiments for a power amplifier that can increase a low-frequency resonance frequency are provided. The power amplifier includes a power amplifying transistor die, a first metal oxide semiconductor capacitor, a direct current decoupling capacitor, and an output matching network, where: a drain of the power amplifying transistor die is connected to a first end of the first metal oxide semiconductor capacitor by using a bonding wire, and a second end of the first metal oxide semiconductor capacitor is grounded; the drain of the power amplifying transistor die is directly connected to the output matching network by using a bonding wire; a source of the power amplifying transistor die is grounded; the first end of the first metal oxide semiconductor capacitor is connected to one end of the direct current decoupling capacitor by using a bonding wire; and the other end of the direct current decoupling capacitor is grounded.
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公开(公告)号：US08916970B2
公开(公告)日：2014-12-23
申请号：US14104237
申请日：2013-12-12
发明人： Lungang Yun , An Huang , Pengbo Tian
IPC分类号： H01L23/48 , H01L21/00 , H01L23/498 , H01L23/00
CPC分类号： H01L23/49811 , H01L24/83 , H01L2924/01322 , H01L2924/1306 , H01L2924/00
摘要： Relating to electronic components, the present disclosure provides a method for welding a gold-silicon eutectic chip, and a transistor. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present disclosure reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.
摘要翻译： 关于电子元件，本公开提供了一种用于焊接金 - 硅共晶芯片和晶体管的方法。 用于焊接金 - 硅共晶芯片的方法包括：在芯片载体的表面上电镀厚度小于或等于1微米的金层; 在焊接区域的金层上粘合多个金突起; 并在共晶温度下在焊接区域中摩擦芯片以形成焊接层。 晶体管包括芯片，芯片载体和连接芯片和芯片载体的中间层，其中焊接中间层是通过使用上述焊接方法获得的焊接层。 本公开减少了使用中的金的量，并且相对较大程度地降低了金 - 硅共晶焊接的成本，并因此降低了晶体管的成本。
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公开(公告)号：US20140175641A1
公开(公告)日：2014-06-26
申请号：US14104237
申请日：2013-12-12
发明人： Lungang Yun , An Huang , Pengbo Tian
IPC分类号： H01L23/498 , H01L21/02
CPC分类号： H01L23/49811 , H01L24/83 , H01L2924/01322 , H01L2924/1306 , H01L2924/00
摘要： Relating to electronic components, the present disclosure provides a method for welding a gold-silicon eutectic chip, and a transistor. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present disclosure reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.
摘要翻译： 关于电子元件，本公开提供了一种用于焊接金 - 硅共晶芯片和晶体管的方法。 用于焊接金 - 硅共晶芯片的方法包括：在芯片载体的表面上电镀厚度小于或等于1微米的金层; 在焊接区域的金层上粘合多个金突起; 并在共晶温度下在焊接区域中摩擦芯片以形成焊接层。 晶体管包括芯片，芯片载体和连接芯片和芯片载体的中间层，其中焊接中间层是通过使用上述焊接方法获得的焊接层。 本公开减少了使用中的金的量，并且相对较大程度地降低了金 - 硅共晶焊接的成本，并因此降低了晶体管的成本。
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