Abstract:
This application discloses a method and an enable apparatus for starting a physical device, where the physical device includes N central processing units (CPUs) and at least one platform controller hub (PCH), N is greater than one. Each of the N CPUs is electrically coupled to a PCH in the at least one PCH. The method includes determining a second CPU in the N CPUs as the primary CPU when a fault occurs in a first CPU, where the first CPU is the primary CPU configured to start the physical device before the fault occurs in the first CPU, and triggering the second CPU as the primary CPU and in cooperation with a first PCH to start the physical device, where the first PCH is one PCH in the at least one PCH.
Abstract:
A node controller-based request responding method and node controller, where the method includes receiving, by a first node controller, a first packet, acquiring an information directory, and querying, in the information directory, whether a memory address requested by the first packet is occupied by a second node controller, and when the memory address requested by the first packet is occupied by the second node controller, querying node presence information to determine whether the second node controller exists, and when it is determined that the second node controller does not exist, generating and sending an invalid response packet.
Abstract:
This application discloses a method and an enable apparatus for starting a physical device, where the physical device includes N central processing units (CPUs) and at least one platform controller hub (PCH), N is greater than one. Each of the N CPUs is electrically coupled to a PCH in the at least one PCH. The method includes determining a second CPU in the N CPUs as the primary CPU when a fault occurs in a first CPU, where the first CPU is the primary CPU configured to start the physical device before the fault occurs in the first CPU, and triggering the second CPU as the primary CPU and in cooperation with a first PCH to start the physical device, where the first PCH is one PCH in the at least one PCH.
Abstract:
A node controller-based request responding method and node controller, where the method includes receiving, by a first node controller, a first packet, acquiring an information directory, and querying, in the information directory, whether a memory address requested by the first packet is occupied by a second node controller, and when the memory address requested by the first packet is occupied by the second node controller, querying node presence information to determine whether the second node controller exists, and when it is determined that the second node controller does not exist, generating and sending an invalid response packet.
Abstract:
The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.
Abstract:
The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.
Abstract:
Embodiments of the present invention disclose a data migration method for memory modules in a server and a server. By establishing a mirror relationship between agent apparatuses of two memory modules, a processor in the present invention instructs the agent apparatuses to perform data migration between the two memory modules, to complete migration of data from one memory module to the other memory module. The entire data migration process requires no participation of an operating system, and consumes a short period of time, thereby implementing convenient data migration for memory modules in a server.