Abstract:
The disclosure relates to technology for pre-fetching data. An apparatus comprises a processor core, pre-fetch logic, and a memory hierarchy. The pre-fetch logic is configured to generate cache pre-fetch requests for a program instruction identified by a program counter. The pre-fetch logic is configured to track one or more statistics with respect to the cache pre-fetch requests. The pre-fetch logic is configured to link the one or more statistics with the program counter. The pre-fetch logic is configured to determine a degree of the cache pre-fetch requests for the program instruction based on the one or more statistics. The memory hierarchy comprises main memory and a hierarchy of caches. The memory hierarchy further comprises a memory controller configured to pre-fetch memory blocks identified in the cache pre-fetch requests from a current level in the memory hierarchy into a higher level of the memory hierarchy.
Abstract:
A data management method comprises a first processing node that obtains a secure storage key based on a first external keying material corresponding to the first processing node, encrypts data corresponding to an application program in the first processing node, and sends encrypted data to a second processing node. The second processing node obtains a secure storage key based on a second external keying material corresponding to the second processing node, and decrypts the encrypted data that corresponds to the application program and that is sent by the first processing node. The second external keying material is the same as the first external keying material, whereby the second processing node and the first processing node may obtain a same secure storage key, and the second processing node may successfully decrypt the encrypted data that corresponds to the application program and that is sent by the first processing node.
Abstract:
The present invention discloses a method for retransmitting a data packet in a quick path interconnect system, and a node. When a first node serves as a sending end, only the first data packet detected to be faulty is retransmitted to a second node, thereby saving system resources that need to be occupied in the data packet retransmission. When the first node serves as a receiving end, it implements that the packet loss does not occur in the first node in a case that the second node only retransmits the second data packet detected to be faulty, thereby ensuring reliability of the data packet transmission based on the QPI bus.
Abstract:
This application discloses a mirrored memory configuration method and apparatus, and a computer storage medium, and belongs to the field of information processing technologies. The method includes the following: After a computer apparatus is started, if the computer apparatus is currently in an OS state and obtains a mirrored memory establishment request, the computer apparatus may switch from the OS state to a BIOS state through system interruption. Then the computer apparatus configures a mirroring relationship in the BIOS state, and switches to the OS state again after configuring the mirroring relationship, to reconfigure a mirrored memory.
Abstract:
A memory data migration method, apparatus, and system are provided. During memory migration, data is classified into two parts based on a hot and cold degree of the data. Hot data is directly migrated, and cold data is written into a shared storage device shared by memories. When needing to be used in a destination-end memory, the cold data may be read from the shared storage device. This reduces an amount of data that needs to be migrated to the destination-end memory, thereby improving memory migration efficiency.
Abstract:
The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.
Abstract:
The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.
Abstract:
Embodiments of the present invention disclose a data migration method for memory modules in a server and a server. By establishing a mirror relationship between agent apparatuses of two memory modules, a processor in the present invention instructs the agent apparatuses to perform data migration between the two memory modules, to complete migration of data from one memory module to the other memory module. The entire data migration process requires no participation of an operating system, and consumes a short period of time, thereby implementing convenient data migration for memory modules in a server.
Abstract:
Embodiments of the present invention disclose a method for accessing a cache and a pseudo cache agent (PCA). The method of the present invention is applied to a multiprocessor system, where the system includes at least one NC, at least one PCA conforming to a processor micro-architecture level interconnect protocol is embedded in the NC, the PCA is connected to at least one PCA storage device, and the PCA storage device stores data shared among memories in the multiprocessor system. The method of the present invention includes: if the NC receives a data request, obtaining, by the PCA, target data required in the data request from the PCA storage device connected to the PCA; and sending the target data to a sender of the data request. Embodiments of the present invention are mainly applied to a process of accessing cache data in the multiprocessor system.
Abstract:
This application discloses a mirrored memory configuration method and apparatus, and a computer storage medium, and belongs to the field of information processing technologies. The method includes the following: After a computer apparatus is started, if the computer apparatus is currently in an OS state and obtains a mirrored memory establishment request, the computer apparatus may switch from the OS state to a BIOS state through system interruption. Then the computer apparatus configures a mirroring relationship in the BIOS state, and switches to the OS state again after configuring the mirroring relationship, to reconfigure a mirrored memory.