公开(公告)号：US20130267073A1

公开(公告)日：2013-10-10

申请号：US13577252

申请日：2012-06-07

申请人： Huaxiang Yin ,  Wei He ,  Huicai Zhong ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Wei He ,  Huicai Zhong ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： The present invention discloses a method of manufacturing a fin field effect transistor, which comprises the steps of forming a plurality of first fin structures on a substrate, which extend along a first direction parallel to the substrate; forming a plurality of second fin structures on a substrate, which extend along a second direction parallel to the substrate and the second direction intersecting with the first direction; selectively removing a part of the second fin structures to form a plurality of gate lines; and selectively removing a part of the first fin structures to form a plurality of substrate lines. In the method of manufacturing a fin field effect transistor according to the present invention, the gate lines and substrate lines are formed simultaneously by first making uniform silicon wing lines and gate wing lines using a limiting photolithography patternizing technique and then performing a centralized cutting of the corresponding specific regions, thereby increasing uniformity and reducing process difficulty and cost.

摘要翻译： 本发明公开了一种制造鳍状场效应晶体管的方法，其特征在于包括以下步骤：沿着平行于衬底的第一方向延伸的衬底上形成多个第一鳍结构; 在基板上形成多个第二翅片结构，所述第二鳍结构沿着平行于所述基板的第二方向延伸并且所述第二方向与所述第一方向相交; 选择性地去除所述第二鳍结构的一部分以形成多个栅极线; 以及选择性地去除所述第一鳍结构的一部分以形成多条基片线。 在根据本发明的鳍状场效应晶体管的制造方法中，通过首先使用限制光刻图案化技术首先制造均匀的硅翼线和栅翼线，然后进行集中切割，同时形成栅极线和衬底线 相应的特定区域，从而增加均匀性，降低工艺难度和成本。

公开(公告)号：US08946071B2

公开(公告)日：2015-02-03

申请号：US14364950

申请日：2012-03-23

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L21/823814 ,  H01L21/2255 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved.

摘要翻译： 本发明公开了一种半导体器件的制造方法，包括：在基板上形成栅叠层结构; 在栅极层叠结构的两侧形成源极/漏极区域和栅极侧壁间隔物; 至少在源/漏区中沉积镍基金属层; 进行第一退火，使得源极/漏极区中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使富Ni相的金属硅化物转变为镍系金属硅化物，同时在镍基金属硅化物与源极/漏极区之间的界面处形成掺杂离子的偏析区域 。 根据本发明的方法在将掺杂离子注入到金属硅化物的富Ni相中之后执行退火，从而提高掺杂离子的固溶度并形成高度浓缩的掺杂离子的偏析区，因此SBH 镍基金属二氧化硅和源极/漏极区域之间的金属 - 半导体接触被有效地降低，接触电阻降低，并且器件的驱动能力得到改善。

公开(公告)号：US20130241004A1

公开(公告)日：2013-09-19

申请号：US13520618

申请日：2012-04-11

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/8236

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是 增强。

公开(公告)号：US08987127B2

公开(公告)日：2015-03-24

申请号：US14361944

申请日：2012-03-23

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

公开(公告)号：US20130240996A1

公开(公告)日：2013-09-19

申请号：US13520611

申请日：2012-04-11

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域 所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层 ，第二功函数金属扩散阻挡层和栅极填充层，功函数接近价带（导带）边; 每个第二栅极堆叠结构包括第二栅极绝缘层，改性的第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，所述第二功函数金属层包括植入功函数调节 掺杂离子，其同时扩散到下面的第一功函数层以调节阈值，使得栅极的功函数接近价带（导带）边缘并与原始第一功函数相反，从而调节 工作功能准确。

公开(公告)号：US20130105763A1

公开(公告)日：2013-05-02

申请号：US13497249

申请日：2011-11-25

申请人： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y99/00

CPC分类号： H01L29/66462 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7785 ,  Y10S977/938

摘要： A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

摘要翻译： 一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。

公开(公告)号：US20140302644A1

公开(公告)日：2014-10-09

申请号：US14361944

申请日：2012-03-23

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L29/66

CPC分类号： H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

公开(公告)号：US08994119B2

公开(公告)日：2015-03-31

申请号：US13520618

申请日：2012-04-11

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/8236 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也 增强。

公开(公告)号：US08816326B2

公开(公告)日：2014-08-26

申请号：US13497249

申请日：2011-11-25

申请人： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/08

CPC分类号： H01L29/66462 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7785 ,  Y10S977/938

摘要： A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

摘要翻译： 一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。

公开(公告)号：US09425288B2

公开(公告)日：2016-08-23

申请号：US14412237

申请日：2012-07-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/268 ,  H01L21/76283 ,  H01L29/665 ,  H01L29/785

摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

摘要翻译： 提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。 沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域 半导体鳍片延伸。 随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源/漏区接触。 本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。