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    Process for fabricating high density memory cells using a polysilicon hard mask
    3.
    发明授权
    Process for fabricating high density memory cells using a polysilicon hard mask 有权
    使用多晶硅硬掩模制造高密度存储单元的方法

    公开(公告)号：US06436766B1

    公开(公告)日：2002-08-20

    申请号：US09430493

    申请日：1999-10-29

    申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.

    摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模优选由多晶硅或硅制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后去除硬掩模，优选使用等离子体蚀刻工艺。

    Integration of an ion implant hard mask structure into a process for fabricating high density memory cells
    4.
    发明授权
    Integration of an ion implant hard mask structure into a process for fabricating high density memory cells 有权
    将离子注入硬掩模结构集成到用于制造高密度存储器单元的工艺中

    公开(公告)号：US06486029B1

    公开(公告)日：2002-11-26

    申请号：US09627563

    申请日：2000-07-28

    申请人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    发明人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

    摘要： A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

    摘要翻译： 一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。 在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。 在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

    Process for fabricating high density memory cells using a metallic hard mask
    5.
    发明授权
    Process for fabricating high density memory cells using a metallic hard mask 有权
    使用金属硬掩模制造高密度记忆单元的方法

    公开(公告)号：US06399446B1

    公开(公告)日：2002-06-04

    申请号：US09429722

    申请日：1999-10-29

    申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/945

    摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.

    摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模由钨，钛或氮化钛制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后将硬掩模剥离，优选使用H 2 O 2溶液。

    Selective contact formation using masking and resist patterning techniques
    8.
    发明授权
    Selective contact formation using masking and resist patterning techniques 有权
    使用掩模和抗蚀剂图案化技术的选择性接触形成

    公开(公告)号：US07622389B1

    公开(公告)日：2009-11-24

    申请号：US11411353

    申请日：2006-04-25

    申请人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    发明人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    IPC分类号： H01L21/302

    CPC分类号： H01L27/11526 ,  H01L27/11548

    摘要： A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.

    摘要翻译： 包括选择性导电触点的半导体器件的制造方法包括在第一和第二存储器件部件上沉积抗蚀剂的步骤，第一和第二部件中的每一个包括形成在衬底中的接合部以及在接合部之间形成在衬底上的栅极。 然后将抗蚀剂从第二部件移除，从而在每个第二部件控制浇口和结上形成抗蚀剂开口。 然后蚀刻抗蚀剂，从而暴露第一组分控制栅极中的每一个，而不暴露围绕第一组分控制栅极的衬底。 然后在暴露的第一部件控制栅极和第二部件控制栅极和结上形成导电触点。