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    Method for producing a shallow trench isolation filled with thermal oxide
    3.
    发明授权
    Method for producing a shallow trench isolation filled with thermal oxide 有权
    用于生产填充有热氧化物的浅沟槽隔离体的方法

    公开(公告)号：US06444539B1

    公开(公告)日：2002-09-03

    申请号：US09784892

    申请日：2001-02-15

    申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    IPC分类号： H01L2176

    CPC分类号： H01L21/7621 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76232

    摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

    摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

    Shallow trench isolation filled with thermal oxide
    4.
    发明授权
    Shallow trench isolation filled with thermal oxide 失效
    浅沟隔离填充热氧化物

    公开(公告)号：US06232646B1

    公开(公告)日：2001-05-15

    申请号：US09082607

    申请日：1998-05-20

    申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    IPC分类号： H01L2900

    CPC分类号： H01L21/7621 ,  H01L21/76232

    摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

    摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

    Process for fabricating high density memory cells using a metallic hard mask
    5.
    发明授权
    Process for fabricating high density memory cells using a metallic hard mask 有权
    使用金属硬掩模制造高密度记忆单元的方法

    公开(公告)号：US06399446B1

    公开(公告)日：2002-06-04

    申请号：US09429722

    申请日：1999-10-29

    申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/945

    摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.

    摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模由钨，钛或氮化钛制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后将硬掩模剥离，优选使用H 2 O 2溶液。

    Integration of an ion implant hard mask structure into a process for fabricating high density memory cells
    6.
    发明授权
    Integration of an ion implant hard mask structure into a process for fabricating high density memory cells 有权
    将离子注入硬掩模结构集成到用于制造高密度存储器单元的工艺中

    公开(公告)号：US06486029B1

    公开(公告)日：2002-11-26

    申请号：US09627563

    申请日：2000-07-28

    申请人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    发明人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

    摘要： A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

    摘要翻译： 一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。 在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。 在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

    Process for fabricating high density memory cells using a polysilicon hard mask
    7.
    发明授权
    Process for fabricating high density memory cells using a polysilicon hard mask 有权
    使用多晶硅硬掩模制造高密度存储单元的方法

    公开(公告)号：US06436766B1

    公开(公告)日：2002-08-20

    申请号：US09430493

    申请日：1999-10-29

    申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.

    摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模优选由多晶硅或硅制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后去除硬掩模，优选使用等离子体蚀刻工艺。