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    Test kit semiconductor package and method of testing semiconductor package using the same
    1.
    发明申请
    Test kit semiconductor package and method of testing semiconductor package using the same 审中-公开
    测试套件半导体封装及使用该半导体封装的半导体封装方法

    公开(公告)号：US20060187647A1

    公开(公告)日：2006-08-24

    申请号：US11347569

    申请日：2006-02-06

    申请人： Hyun-Guen Iy ,  Jeong-Ho Bang ,  Hyun-Seop Shim ,  Jae-il Lee ,  Kum-Jin Yun

    发明人： Hyun-Guen Iy ,  Jeong-Ho Bang ,  Hyun-Seop Shim ,  Jae-il Lee ,  Kum-Jin Yun

    IPC分类号： H05K7/20

    CPC分类号： H05K7/1061 ,  G01R31/2863 ,  G01R31/2893

    摘要： A test kit for a semiconductor package and a method of testing a semiconductor package using the same are provided. The test kit may include a pick-and-place tool for loading/unloading a semiconductor package, a head assembly for guiding a semiconductor package released from the pick-and-place tool, and a socket for receiving the semiconductor package from the pick-and-place tool. The method may include performing pre-alignment by inserting one or more slide posts of an alignment tool into a socket, releasing a semiconductor package through a package guider, and attaching the semiconductor package onto a socket.

    摘要翻译： 提供一种用于半导体封装的测试套件以及使用其的半导体封装测试方法。 测试套件可以包括用于加载/卸载半导体封装的拾取和放置工具，用于引导从拾取和放置工具释放的半导体封装的头组件和用于从拾取放置工具接收半导体封装的插座， 放置工具。 该方法可以包括通过将对准工具的一个或多个滑动柱插入插座来执行预对准，通过封装导向器释放半导体封装，以及将半导体封装连接到插座上。

    Connector for testing a semiconductor package
    3.
    发明申请
    Connector for testing a semiconductor package 有权
    用于测试半导体封装的连接器

    公开(公告)号：US20060121757A1

    公开(公告)日：2006-06-08

    申请号：US11295208

    申请日：2005-12-05

    申请人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

    发明人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

    IPC分类号： H01R4/58

    CPC分类号： G01R1/0483 ,  G01R1/045 ,  G01R1/0466 ,  G01R31/2863

    摘要： In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.

    摘要翻译： 在一个实施例中，使用绝缘硅氧烷粉末和导电粉末的混合物制造连接器。 连接器包括由绝缘硅氧烷粉末形成的连接器主体，并且通过将导电粉末迁移到对应于半导体封装的焊料球的连接部位而形成的或更优选地规则排列的导电硅树脂构件。 导电硅树脂构件包括形成为接近连接器主体的上表面并从其突出的高密度导电硅树脂部件，以及在高密度导电硅树脂部件下方大致垂直取向地形成的低密度导电硅树脂部件， 低密度导电硅部件，其具有从连接器本体的下表面露出的下表面。

    Connector for testing a semiconductor package
    5.
    发明授权
    Connector for testing a semiconductor package 有权
    用于测试半导体封装的连接器

    公开(公告)号：US07438563B2

    公开(公告)日：2008-10-21

    申请号：US11295208

    申请日：2005-12-05

    申请人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

    发明人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

    IPC分类号： H01R4/58

    CPC分类号： G01R1/0483 ,  G01R1/045 ,  G01R1/0466 ,  G01R31/2863

    摘要： In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.

    摘要翻译： 在一个实施例中，使用绝缘硅氧烷粉末和导电粉末的混合物制造连接器。 连接器包括由绝缘硅氧烷粉末形成的连接器主体，并且通过将导电粉末迁移到对应于半导体封装的焊料球的连接部位而形成的或更优选地规则排列的导电硅树脂构件。 导电硅树脂构件包括形成为接近连接器主体的上表面并从其突出的高密度导电硅树脂部件和在高密度导电硅树脂部件下方基本上垂直取向形成的低密度导电硅树脂部件， 低密度导电硅部件，其具有从连接器本体的下表面露出的下表面。

    Apparatus and method for performing parallel test on integrated circuit devices
    8.
    发明申请
    Apparatus and method for performing parallel test on integrated circuit devices 有权
    在集成电路设备上执行并行测试的装置和方法

    公开(公告)号：US20050007140A1

    公开(公告)日：2005-01-13

    申请号：US10856461

    申请日：2004-05-27

    申请人： Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    发明人： Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    IPC分类号： G01R31/28 ,  G01R31/319 ,  G11C29/00 ,  G01R31/26

    CPC分类号： G01R31/31905 ,  G11C2029/2602

    摘要： Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

    摘要翻译： 本发明的实施例以并行方式连接多个待测器件（DUTS），并且将高测试电流选择性地施加到每个DUT。 测试多个DUT的装置包括向多个DUT提供测试电流的多个电源; 以及连接到各个DUT和电源的开关装置，并选择性地提供测试电流。 此外，该装置具有至少一个控制单元来控制开关装置。 此外，来自多个DUT的一组DUT以并行方式连接在多个电源中的两个之间，并且根据开关装置的操作，从DUT组中选择性地向一个DUT提供测试电流。

    Apparatus and method for performing parallel test on integrated circuit devices
    9.
    发明授权
    Apparatus and method for performing parallel test on integrated circuit devices 有权
    在集成电路设备上执行并行测试的装置和方法

    公开(公告)号：US07227351B2

    公开(公告)日：2007-06-05

    申请号：US10856461

    申请日：2004-05-27

    申请人： Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    发明人： Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31905 ,  G11C2029/2602

    摘要： Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

    摘要翻译： 本发明的实施例以并行方式连接多个待测器件（DUTS），并且将高测试电流选择性地施加到每个DUT。 测试多个DUT的装置包括向多个DUT提供测试电流的多个电源; 以及连接到各个DUT和电源的开关装置，并选择性地提供测试电流。 此外，该装置具有至少一个控制单元来控制开关装置。 此外，来自多个DUT的一组DUT以并行方式连接在多个电源中的两个之间，并且根据开关装置的操作，从DUT组中选择性地向一个DUT提供测试电流。

    Test board of semiconductor tester having modified input/output printed circuit pattern and testing method using the same
    10.
    发明申请
    Test board of semiconductor tester having modified input/output printed circuit pattern and testing method using the same 审中-公开
    具有修改的输入/输出印刷电路图案的半导体测试仪测试板及使用其的测试方法

    公开(公告)号：US20060085715A1

    公开(公告)日：2006-04-20

    申请号：US11243053

    申请日：2005-10-03

    申请人： Yong-Woon Kim ,  Jeong-Ho Bang ,  Hyun-Seop Shim ,  Woo-Ik Park

    发明人： Yong-Woon Kim ,  Jeong-Ho Bang ,  Hyun-Seop Shim ,  Woo-Ik Park

    IPC分类号： G06F11/00

    CPC分类号： G01R31/31723 ,  G01R31/31905 ,  G06F11/2733

    摘要： A test board for a semiconductor device tester having a modified input/output printed circuit pattern and a testing method using the same are provided. In an embodiment, a modified input/output printed circuit pattern is formed and controlled by a test program, wherein the modified input/output printed circuit pattern is divided into a drive terminal and a comparator terminal, one of the terminals being connected to one input pin of a device under test (DUT) and the other being connected to an output pin of the DUT, unlike a typical input/output printed circuit pattern of the test board that is formed to be connected to one output pin of a DUT. Thus, it is possible to increase the number of devices under parallel test and to test semiconductor memory devices having larger capacity by using limited resources of the tester.

    摘要翻译： 提供了一种具有改进的输入/输出印刷电路图案的半导体器件测试器的测试板和使用其的测试方法。 在一个实施例中，修改的输入/输出印刷电路图案由测试程序形成和控制，其中修改的输入/输出印刷电路图案被分成驱动端子和比较器端子，其中一个端子连接到一个输入端 与被测设备（DUT）的引脚，另一个连接到DUT的输出引脚，与形成为连接到DUT的一个输出引脚的测试板的典型输入/输出印刷电路图案不同。 因此，可以增加并行测试下的器件数量，并且通过使用测试器的有限资源来测试具有较大容量的半导体存储器件。