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    Phase change memory device providing compensation for leakage current
    1.
    发明申请
    Phase change memory device providing compensation for leakage current 有权
    提供漏电流补偿的相变存储器件

    公开(公告)号：US20060181915A1

    公开(公告)日：2006-08-17

    申请号：US11319266

    申请日：2005-12-29

    申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

    发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

    摘要： A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.

    摘要翻译： 半导体存储器件包括连接到同一位线和不同相应字线的多个相变存储器单元。 通过选择位线和相应的字线，对存储器单元之一执行读取操作。 在执行读取操作的同时，由漏电检测电路检测由未选择的存储单元产生的漏电流，并由泄漏电流供给电路进行补偿。

    Magneto-resistive RAM having multi-bit cell array structure
    2.
    发明申请
    Magneto-resistive RAM having multi-bit cell array structure 有权
    具有多位单元阵列结构的磁阻RAM

    公开(公告)号：US20060092690A1

    公开(公告)日：2006-05-04

    申请号：US11260602

    申请日：2005-10-27

    申请人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C11/00

    CPC分类号： H03L7/0812 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H03L7/0891

    摘要： A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.

    摘要翻译： 具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。 第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。 第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。 第一至第三电阻可变元件具有相等的电阻。

    Phase change memory device providing compensation for leakage current
    3.
    发明授权
    Phase change memory device providing compensation for leakage current 有权
    提供漏电流补偿的相变存储器件

    公开(公告)号：US07245526B2

    公开(公告)日：2007-07-17

    申请号：US11319266

    申请日：2005-12-29

    申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

    发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

    摘要： A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.

    摘要翻译： 半导体存储器件包括连接到同一位线和不同相应字线的多个相变存储器单元。 通过选择位线和相应的字线，对存储器单元之一执行读取操作。 在执行读取操作的同时，由漏电检测电路检测由未选择的存储单元产生的漏电流，并由泄漏电流供给电路进行补偿。

    Magneto-resistive RAM having multi-bit cell array structure
    4.
    发明授权
    Magneto-resistive RAM having multi-bit cell array structure 有权
    具有多位单元阵列结构的磁阻RAM

    公开(公告)号：US07463509B2

    公开(公告)日：2008-12-09

    申请号：US11260602

    申请日：2005-10-27

    申请人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C11/00

    CPC分类号： H03L7/0812 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H03L7/0891

    摘要： A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.

    摘要翻译： 具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。 第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。 第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。 第一至第三电阻可变元件具有相等的电阻。

    Resistance random access memory having common source line
    5.
    发明授权
    Resistance random access memory having common source line 有权
    具有共同源极线的电阻随机存取存储器

    公开(公告)号：US07903448B2

    公开(公告)日：2011-03-08

    申请号：US11964142

    申请日：2007-12-26

    申请人： Hyung-Rok Oh ,  Sang-Beom Kang ,  Joon-Min Park ,  Woo-Yeong Cho

    发明人： Hyung-Rok Oh ,  Sang-Beom Kang ,  Joon-Min Park ,  Woo-Yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/79

    摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.

    摘要翻译： 具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。 其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个 源线。 存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。 存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。 多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。 在存储单元写入操作中，将正电压施加到源极线。 通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

    Phase-changeable memory device and read method thereof
    6.
    发明授权
    Phase-changeable memory device and read method thereof 有权
    相变存储器件及其读取方法

    公开(公告)号：US07391644B2

    公开(公告)日：2008-06-24

    申请号：US11605212

    申请日：2006-11-29

    申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

    摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

    Semiconductor memory device and method for reducing cell activation during write operations
    7.
    发明授权
    Semiconductor memory device and method for reducing cell activation during write operations 有权
    用于在写入操作期间减少电池激活的半导体存储器件和方法

    公开(公告)号：US07542356B2

    公开(公告)日：2009-06-02

    申请号：US11790146

    申请日：2007-04-24

    申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

    摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

    摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

    Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature
    8.
    发明授权
    Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature 有权
    写入驱动电路，用于根据环境温度控制施加到相变存储器的写入电流

    公开(公告)号：US07447092B2

    公开(公告)日：2008-11-04

    申请号：US11079198

    申请日：2005-03-15

    申请人： Baek-Hyung Cho ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Byung-Gil Choi

    发明人： Baek-Hyung Cho ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Byung-Gil Choi

    IPC分类号： G11C7/04

    CPC分类号： G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0078

    摘要： A programming method which controls the amount of a write current applied TO Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the phase change material (PCM) in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing or keeping the same a reset current and/or a set current.

    摘要翻译： 控制施加到TO相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。 编程方法包括保持在较高电阻状态下的PCM的电阻与相变材料（PCM）的电阻在较低电阻状态下的比率恒定或基本恒定，而与环境温度无关。 可以通过增加，减少或保持复位电流和/或设定电流来保持该比率。