摘要:
A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.
摘要:
A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.
摘要:
A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.
摘要:
A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.
摘要:
A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要:
A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要:
A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要:
A magnetic random access memory device includes a digit line, a bit line, and a magnetic memory cell disposed in an intersection between the digit line and the bit line. The digit line is extended in a first direction on a substrate. The bit line is extended in a second direction on the substrate. The magnetic memory cell includes a rectangular free magnetic layer magnetized in a direction according to an externally applied magnetic field. A major axis of the rectangular free magnetic layer is substantially parallel to the first direction, and a minor axis of the rectangular free magnetic layer is substantially parallel to the second direction. Thus, multiple input/output program (write) operations and multiple input/output repair operations may be effectively performed.
摘要:
A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.
摘要:
A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.