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    Method of fabricating semiconductor device using a work function control film
    1.
    发明授权
    Method of fabricating semiconductor device using a work function control film 有权
    使用功能控制膜制造半导体器件的方法

    公开(公告)号：US08580629B2

    公开(公告)日：2013-11-12

    申请号：US13241871

    申请日：2011-09-23

    申请人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

    发明人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

    摘要： A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.

    摘要翻译： 制造半导体器件的方法可以包括：制备其中限定了第一和第二区域的衬底; 在衬底上形成包括第一和第二沟槽的层间绝缘膜; 沿着层间绝缘膜的上表面，第一沟槽的侧表面和底表面以及第二沟槽的侧表面和底表面形成包含Al和N的功函数控制膜; 在形成在第二区域中的功函数控制膜上形成掩模图案; 将工作功能控制材料注入到形成在第一区域中的功函数控制膜中，以控制形成在第一区域中的功函数控制膜的功函数; 去除掩模图案; 以及形成第一金属栅电极以填充所述第一沟槽并形成第二金属栅电极以填充所述第二沟槽。

    Semiconductor device and method of fabricating the same
    5.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08786028B2

    公开(公告)日：2014-07-22

    申请号：US13445667

    申请日：2012-04-12

    申请人： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

    发明人： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823437 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

    摘要： A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.

    摘要翻译： 制造半导体器件的方法，半导体器件和结合其的系统包括掺杂有杂质的栅极金属的晶体管。 晶体管的改变的功函数可以改变晶体管的阈值电压。 在某些实施例中，第一MOSFET的栅极金属掺杂有杂质。 第二MOSFET的栅极金属可以不掺杂，掺杂有不同浓度的相同杂质和/或掺杂有不同杂质。 在一些实施例中，MOSFET是FinFET，并且掺杂可以是共形掺杂。

    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120280330A1

    公开(公告)日：2012-11-08

    申请号：US13422106

    申请日：2012-03-16

    申请人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Sang-Bom Kang ,  Jae-Jung Kim

    发明人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Sang-Bom Kang ,  Jae-Jung Kim

    IPC分类号： H01L27/088

    CPC分类号： H01L27/0886 ,  H01L21/823431

    摘要： Semiconductor devices including first and second fin active regions protruding vertically from a substrate and integrally formed with the substrate, a gate insulation layer formed on the first and second fin active regions, a first gate metal contacting the gate insulation layer on the first fin active region, and a second gate metal contacting the first gate metal on the first fin active region and contacting the gate insulation layer on the second fin active region.

    摘要翻译： 半导体器件包括从基板垂直突出并与基板一体形成的第一和第二鳍状物活性区域，形成在第一和第二鳍状物活性区域上的栅极绝缘层，与第一鳍状物活性区域上的栅极绝缘层接触的第一栅极金属 以及第二栅极金属，其与第一鳍状物活性区域上的第一栅极金属接触并且接触第二鳍状物活性区域上的栅极绝缘层。

    MOS transistor and method of manufacturing the same
    10.
    发明申请
    MOS transistor and method of manufacturing the same 审中-公开
    MOS晶体管及其制造方法

    公开(公告)号：US20070057333A1

    公开(公告)日：2007-03-15

    申请号：US11519063

    申请日：2006-09-12

    申请人： Hong-Bae Park ,  Yu-Gyun Shin

    发明人： Hong-Bae Park ,  Yu-Gyun Shin

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/4925 ,  H01L29/517

    摘要： Example embodiments relate to a metal-oxide-semiconductor (MOS) transistor and a method of manufacturing the MOS transistor. In a MOS transistor and a method of manufacturing the same, a gate insulation layer may be formed on the channel region of the substrate, and may further include metal oxide or metal silicate. A buffer layer may be formed on the gate insulation layer. The buffer layer may further include any one selected from the group including silicon nitride, aluminum nitride, undoped polysilicon and combinations thereof. A gate conductive layer may be formed on the buffer layer and may further include polysilicon. The buffer layer may retard or prevent a reaction between the gate conductive layer and the gate insulation layer. Source/drain regions may be further formed at surface portions of the substrate and doped with impurities. A channel region may also be further formed at the surface portion of the substrate between the source/drain regions.

    摘要翻译： 示例性实施例涉及金属氧化物半导体（MOS）晶体管和制造MOS晶体管的方法。 在MOS晶体管及其制造方法中，可以在衬底的沟道区上形成栅极绝缘层，还可以包括金属氧化物或金属硅酸盐。 可以在栅极绝缘层上形成缓冲层。 缓冲层可以进一步包括从包括氮化硅，氮化铝，未掺杂的多晶硅及其组合的组中选择的任一种。 栅极导电层可以形成在缓冲层上，并且还可以包括多晶硅。 缓冲层可以延迟或防止栅极导电层和栅极绝缘层之间的反应。 源极/漏极区域可以进一步形成在衬底的表面部分并掺杂杂质。 还可以在源极/漏极区之间的衬底的表面部分处进一步形成沟道区。