公开(公告)号：US3144366A

公开(公告)日：1964-08-11

申请号：US13177161

申请日：1961-08-16

Applicant: IBM

Inventor： RIDEOUT ARTHUR J ,  WORTHINGTON THOMAS K

IPC: C23C14/04 ,  H01L21/00 ,  H01L21/316 ,  H01L29/00

CPC classification number: H01L21/00 ,  C23C14/042 ,  H01L21/02164 ,  H01L21/02269 ,  H01L21/31612 ,  H01L29/00 ,  Y10S148/106 ,  Y10S148/169

公开(公告)号：US3611062A

公开(公告)日：1971-10-05

申请号：US3611062D

申请日：1968-04-17

Applicant: IBM

Inventor： RIDEOUT ARTHUR J

IPC: H01L21/00 ,  H01L21/82 ,  H01L27/08 ,  H01L5/02

CPC classification number: H01L27/0805 ,  H01L21/00 ,  H01L21/82 ,  Y10S148/106 ,  Y10S148/136 ,  Y10S148/145 ,  Y10S148/151 ,  Y10S148/167

Abstract: A capacitor is formed for a monolithic integrated circuit with an increased capacitance without a decrease in breakdown voltage by forming the junction in a plurality of curved portions rather than a straight portion. The junction may be formed by either a single or double diffusion through parallel slots in a mask to permit diffusion. It also may be formed by either a single or double diffusion through orthogonal families of parallel slots. A resistor is formed by two diffusions to form the junction rather than a single diffusion whereby the gradient of the doping profile in the depletion layer of the junction is reduced. This reduces the parasitic capacitance at the junction for a given resistance whereby the resistor may be utilized at a higher cutoff frequency to permit the resistor to be utilized in higher frequency circuits.

公开(公告)号：US3195218A

公开(公告)日：1965-07-20

申请号：US21988062

申请日：1962-08-28

Applicant: IBM

Inventor： MILLER WILLIAM H ,  RIDEOUT ARTHUR J ,  WORTHINGTON THOMAS K

IPC: H01L21/00 ,  H01L21/322 ,  H01L23/29 ,  H01L29/00

CPC classification number: H01L23/291 ,  H01L21/00 ,  H01L21/3221 ,  H01L29/00 ,  H01L2224/4847 ,  Y10S438/904 ,  Y10S438/938

公开(公告)号：US3656034A

公开(公告)日：1972-04-11

申请号：US3656034D

申请日：1970-01-20

Applicant: IBM

Inventor： RIDEOUT ARTHUR J

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L27/00 ,  H01L11/06

CPC classification number: H01L21/74 ,  H01L27/00 ,  Y10S148/032 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/096

Abstract: An integrated lateral transistor which is easily made symmetrical. An NPN embodiment is constructed on a P- substrate which forms PN junctions with an adjacent N+ buried region and an N epitaxial region within which the N+ region is located. Integral with the substrate is a P+ isolation region which extends to the upper surface of the semiconductor to isolate the N epitaxial layer from adjacent devices. A base region is diffused into the epitaxial region to form a PN junction with the N+ buried region. N+ emitter and collector regions are diffused into the P type base region until the junctions they form with the base are within much less than one diffusion length of the base-buried region PN junction. The emitter and collector are also within two minority carrier diffusion lengths of each other. A similar PNP embodiment is also disclosed.

Abstract translation: 一个易于对称的集成横向晶体管。 NPN实施例构造在P-衬底上，其与相邻的N +掩埋区域和N +区域所在的N外延区域形成PN结。 与衬底成一体是P +隔离区，其延伸到半导体的上表面以将N外延层与相邻器件隔离。 基极区域扩散到外延区域中以与N +掩埋区域形成PN结。 N +发射极和集电极区域扩散到P型基极区域中，直到它们与基极形成的结为远远小于基极掩埋区PN结的一个扩散长度。 发射极和集电极也在彼此的两个少数载流子扩散长度内。 还公开了类似的PNP实施例。

公开(公告)号：US3650854A

公开(公告)日：1972-03-21

申请号：US3650854D

申请日：1970-08-03

Applicant: IBM

Inventor： DEMSKY HERBERT M ,  PLATT ALAN ,  RIDEOUT ARTHUR J ,  SAMSON ROBERT S

IPC: H01L21/00 ,  H01L21/22 ,  H01L29/00 ,  H01L29/73 ,  H01L7/44

CPC classification number: H01L29/00 ,  H01L21/00 ,  H01L21/22 ,  H01L29/73 ,  Y10S148/043 ,  Y10S148/106

Abstract: A process for producing in a transistor a slumped base profile wherein the base diffusion window is reoxidized, a layer of P2O5 is deposited over the oxide, an insulating layer deposited over the P2O5, an emitter window opened, and emitter diffusion made.

Abstract translation: 一种用于在晶体管中制造贱底基本轮廓的方法，其中基底扩散窗被再氧化，在氧化物上沉积P2O5层，沉积在P2O5上的绝缘层，打开的发射器窗口和发射极扩散。