公开(公告)号：US20220176136A1

公开(公告)日：2022-06-09

申请号：US17546616

申请日：2021-12-09

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Yao-Hong Liu ,  Barundeb Dutta

IPC: A61N1/372 ,  A61N1/05 ,  A61B5/00

Abstract: The present disclosure relates to a brain-computer interface system and method. In an example, a brain-computer interface system includes a data processing unit, a data transceiver unit, and a sensing or stimulation unit. The system also includes a first communication path between the data transceiver unit and the sensing or stimulation unit including a first downlink channel for transmitting power and data from the data transceiver unit to the data sensing unit and a first uplink channel for transmitting data from the sensing or stimulation unit to the data transceiver unit. The system may additionally include a second communication path between the data processing unit and the data transceiver unit including a second downlink channel for transmitting power and data from the data processing unit to the data transceiver unit and a second uplink channel for transmitting data from the data transceiver unit to the data processing unit.

公开(公告)号：US20150115277A1

公开(公告)日：2015-04-30

申请号：US14520763

申请日：2014-10-22

Applicant: IMEC VZW

Inventor： Vasyl Motsnyi ,  Barundeb Dutta ,  Maarten Rosmeulen

IPC: H01L29/20 ,  H01L33/12 ,  H01L21/306 ,  H01L29/201 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L29/2003 ,  B24B37/042 ,  H01L21/02002 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30625 ,  H01L29/201 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32

Abstract: The embodiments disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate. A first layer formed atop the silicon substrate, is subsequently patterned to expose the underlying silicon substrate. A group III-V material layer is formed over the patterned first layer and also on the exposed silicon substrate. The group III-V material layer is subjected to chemical mechanical polishing (CMP) to expose the first layer resulting in the formation of a plurality of areas suitable for growing a device layer on the silicon substrate.

Abstract translation: 实施方式公开了具有III-V族材料的硅衬底和在硅衬底上制造III-V族材料的方法。 该方法包括提供硅衬底。 形成在硅衬底顶上的第一层随后被图案化以暴露下面的硅衬底。 在图案化的第一层上以及暴露的硅衬底上形成III-V族材料层。 对III-V族材料层进行化学机械抛光（CMP）以暴露第一层，从而形成适于在硅衬底上生长器件层的多个区域。