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公开(公告)号：US12037568B2
公开(公告)日：2024-07-16
申请号：US17128091
申请日：2020-12-19
Applicant: IMEC VZW , Katholieke Universiteit Leuven
Inventor： Aaron Delahanty , Dries Braeken , Alexandru Andrei , Peter Peumans , Carolina Mora Lopez , Veerle Reumers , Veronique Rochus , Bart Weekers
CPC classification number: C12M1/34 , C12N1/00 , C12N2513/00
Abstract: A semiconductor cell culture device for three-dimensional cell culture comprises: a semiconductor material layer in which a cell culture portion of semiconductor material is defined, wherein the cell culture portion defines an area within the semiconductor material layer surrounded by semiconductor material, wherein the cell culture portion comprises a mesh structure having island structures being interconnected by bridge structures and defining through-pores between the island structures allowing for selective transport of cell constructs, cellular components, proteins or other large molecules through the semiconductor material layer and on opposite sides of the cell culture portion in the semiconductor material layer, and a supporting structure connected to the cell culture portion.
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公开(公告)号：US11609223B2
公开(公告)日：2023-03-21
申请号：US16035574
申请日：2018-07-13
Applicant: IMEC VZW
Inventor： Carolina Mora Lopez
IPC: G01N33/483 , G01N27/414 , H03F3/45 , B01L3/00 , B01J19/00
Abstract: A device for analysis of cells comprises: an active sensor area (104) presenting a surface for cell growth; a microelectrode array (102) comprising a plurality of pixels (110) in the active sensor area (104), wherein each pixel (110) comprises at least one electrode (120) at the surface, wherein each pixel (110) is configured to control the configuration of the pixel circuitry and set a measurement modality of the pixel; recording circuitry having a plurality of recording channels (130), wherein each pixel (110) is connected to a recording channel (130), wherein each recording channel (130) comprises a reconfigurable component (131), which is selectively controlled between being set to a first mode, in which the reconfigurable component (131) is configured to amplify a received pixel signal, and being set to a second mode, in which the reconfigurable component (131) is configured to selectively pass a frequency band of the received pixel signal.
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3.发明申请公开(公告)号：US20250073450A1
公开(公告)日：2025-03-06
申请号：US18818054
申请日：2024-08-28
Applicant: IMEC VZW
Inventor： Chutham Sawigun , Carolina Mora Lopez , Xiaolin Yang , Joan Aymerich
Abstract: The present disclosure provides a neuromodulation device that comprises at least one amplifier circuit that suppresses a common mode (CM) voltage signal in the input voltage signal. The amplifier circuit comprises an input stage to receive the input voltage signal, and a differential transconductor to provide an output current signal based on a DM voltage signal in the input voltage signal. The transconductor is provides a first CM voltage signal tapped after a non-inverting input, and a second CM voltage signal tapped after am inverting input, to CM amplifier of the amplifier circuit. The CM amplifier combines the first CM voltage signal with the second CM voltage signal, amplifies the combined CM voltage signal with an inverting gain, and provides the inverted CM voltage signal back to the non-inverting input and the inverting input of the transconductor for enabling the CM suppression.
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公开(公告)号：US20230201573A1
公开(公告)日：2023-06-29
申请号：US18068045
申请日：2022-12-19
Applicant: IMEC VZW , Universiteit Gent
Inventor： Denys Nikolayev , Wout Joseph , Luc Martens , Alexandru Andrei , Carolina Mora Lopez , Emmeric Tanghe
CPC classification number: A61N1/0529 , H01B5/14 , H01B13/0036
Abstract: A method includes providing a first electrically conductive element over a top surface of a substrate. The method includes measuring at least one parameter indicative of the shape or dimensions of the first electrically conductive element. The method includes simulating the first electrically conductive element and a dielectric wall surrounding the first electrically conductive element for a plurality of wall heights by using the at least one parameter as an input. The method includes for each wall height, computing the maximum current density present at a surface of the first electrically conductive element. The method includes determining, from the maximum current densities, wall height(s) for which the maximum current density is below a threshold. Furthermore, the method includes providing a second electrically conductive element, identical to the first electrically conductive element, surrounded by a wall having a wall height of the determined wall height(s).
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Patent Agency Ranking
公开(公告)号：US20240288415A1
公开(公告)日：2024-08-29
申请号：US18589666
申请日：2024-02-28
Applicant: IMEC VZW
Inventor： Carolina Mora Lopez
IPC: G01N33/483
CPC classification number: G01N33/4836
Abstract: The present disclosure provides a device for processing biological material that includes: an array of pixels including one or more rows of pixels; a data controller; a plurality of electrical interconnections configured for bi-directional communication between neighboring pixel circuits within a row, between the data controller and the pixel circuit of the first pixel of each row, and between the data controller and the pixel circuit of the last pixel of each row. Methods and computer systems for processing biological material are also provided.
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公开(公告)号：US11583679B2
公开(公告)日：2023-02-21
申请号：US17031733
申请日：2020-09-24
Applicant: IMEC VZW
Inventor： Carolina Mora Lopez , Marco Ballini , Didac Gomez Salinas
Abstract: An electrode arrangement for stimulating and recording electrical signals in biological matter comprises: an array (110) of electrodes (112), wherein electrodes (112) are configured to be switchable between stimulating and recording of electrical signals; a control unit (120), wherein the control unit (120) is configured to select a plurality of electrodes (112) to form a combined macroelectrode site (114) for providing a stimulating signal, wherein the control unit (120) is further configured to determine a perimeter electrode (112b) and a central electrode (112a), wherein the perimeter electrode (112b) is arranged at a perimeter of the combined macroelectrode site (114) and the central electrode (112a) is arranged centrally within the combined macroelectrode site (114), and wherein the control unit (120) is further configured to provide a stimulation signal to the perimeter electrode (112b) that has a lower magnitude than a stimulation signal provided to the central electrode (112a).
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7.发明授权公开(公告)号：US10811542B2
公开(公告)日：2020-10-20
申请号：US16176448
申请日：2018-10-31
Applicant: IMEC VZW
Inventor： Carolina Mora Lopez
IPC: H01L29/8605 , H01L27/07 , H01L29/06 , H03F3/45 , H01L29/861 , G01N27/04 , A61B5/04
Abstract: A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.
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公开(公告)号：US10044325B2
公开(公告)日：2018-08-07
申请号：US15380021
申请日：2016-12-15
Applicant: IMEC VZW
Inventor： Carolina Mora Lopez , Srinjoy Mitra
Abstract: An amplifier circuit, a voltage sensing apparatus, and an amplification method are disclosed. The amplifier circuit comprises (1) an input stage comprising a first set of transistors to which an input signal to be amplified is applied, the transistors of the first set comprising a semiconductor body, and (2) a processing stage comprising a second set of transistors for processing the signal from the input stage and generating an output signal. The transistors of the first set have a thicker gate oxide than the transistors of the second set, and are therefore suitable for higher voltage operation. The first and second sets of transistors are supplied by the same voltage supply of the amplifier circuit. The semiconductor body of the first set of transistors is connected to a reference potential to lower the threshold voltage.
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公开(公告)号：US20170179891A1
公开(公告)日：2017-06-22
申请号：US15380021
申请日：2016-12-15
Applicant: IMEC VZW
Inventor： Carolina Mora Lopez , Srinjoy Mitra
CPC classification number: H03F1/26 , A61B5/04001 , H03F1/0261 , H03F3/45179 , H03F3/45183 , H03F3/45188 , H03F3/45192 , H03F3/45475 , H03F2200/171 , H03F2200/261 , H03F2200/513 , H03F2203/45136 , H03F2203/45342 , H03F2203/45526
Abstract: An amplifier circuit, a voltage sensing apparatus, and an amplification method are disclosed. The amplifier circuit comprises (1) an input stage comprising a first set of transistors to which an input signal to be amplified is applied, the transistors of the first set comprising a semiconductor body, and (2) a processing stage comprising a second set of transistors for processing the signal from the input stage and generating an output signal. The transistors of the first set have a thicker gate oxide than the transistors of the second set, and are therefore suitable for higher voltage operation. The first and second sets of transistors are supplied by the same voltage supply of the amplifier circuit. The semiconductor body of the first set of transistors is connected to a reference potential to lower the threshold voltage.
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