公开(公告)号：US20180101483A1

公开(公告)日：2018-04-12

申请号：US15726749

申请日：2017-10-06

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Matthias Hartmann ,  Jose Ignacio Gomez ,  Christian Tenllado ,  Sotiris Xydis ,  Javier Setoain Rodrigo ,  Thomas Papastergiou ,  Christos Baloukas ,  Anup Kumar Das ,  Dimitrios Soudris

IPC: G06F12/1045 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/128

CPC classification number: G06F12/1054 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/122 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/2515 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/621 ,  G06F2212/652 ,  Y02D10/13

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

公开(公告)号：US20240202506A1

公开(公告)日：2024-06-20

申请号：US18541268

申请日：2023-12-15

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Paul Detterer ,  Emmanouil Sifalakis ,  Federico Corradi ,  Matthias Hartmann

IPC: G06N3/049

CPC classification number: G06N3/049

Abstract: The present disclosure relates to a computer-implemented method for controlling the firing of neurons within a neuron layer of a spiking neural network. The method includes, by a handshake controller associated with the neuron layer, receiving a request for firing the neurons and, in response, generating a tick signal. The method further comprising, by the respective neurons, updating a neuron state when receiving a neuron input; and upon receiving the tick signal, by the respective neurons, firing the respective neurons that fulfil a firing condition based on the neuron state.

公开(公告)号：US10019361B2

公开(公告)日：2018-07-10

申请号：US15250188

申请日：2016-08-29

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Matthias Hartmann ,  Komalan Manu Perumkunnil ,  Jose Ignacio Gomez ,  Christian Tenllado

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/0897 ,  G11C7/10 ,  G11C11/16 ,  G06F15/78 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0685 ,  G06F3/0688 ,  G06F8/41 ,  G06F8/452 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/0897 ,  G06F13/1657 ,  G06F13/1673 ,  G06F15/781 ,  G06F15/7846 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/454 ,  G06F2212/601 ,  G06F2212/6028 ,  G11C7/10 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675

Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.

公开(公告)号：US10592430B2

公开(公告)日：2020-03-17

申请号：US15726749

申请日：2017-10-06

Applicant: IMEC VZW ,  Stichting IMEC Nederland ,  UNIVERSIDAD COMPLUTENSE DE MADRID

Inventor： Francky Catthoor ,  Matthias Hartmann ,  Jose Ignacio Gomez ,  Christian Tenllado ,  Sotiris Xydis ,  Javier Setoain Rodrigo ,  Thomas Papastergiou ,  Christos Baloukas ,  Anup Kumar Das ,  Dimitrios Soudris

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/128 ,  G06F12/0864 ,  G06F12/08 ,  G06F12/02

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

公开(公告)号：US20170091094A1

公开(公告)日：2017-03-30

申请号：US15250188

申请日：2016-08-29

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Matthias Hartmann ,  Komalan Manu Perumkunnil ,  Jose Ignacio Gomez ,  Christian Tenllado

IPC: G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/0811 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0685 ,  G06F3/0688 ,  G06F8/41 ,  G06F8/452 ,  G06F9/30036 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/0897 ,  G06F13/1657 ,  G06F13/1673 ,  G06F15/781 ,  G06F15/7846 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/454 ,  G06F2212/601 ,  G06F2212/6028 ,  G11C7/10 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675

Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.