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    PLASMA ETCHING OF POROUS SUBSTRATES
    2.
    发明申请
    PLASMA ETCHING OF POROUS SUBSTRATES 有权
    等离子体蚀刻多孔基板

    公开(公告)号：US20160276133A1

    公开(公告)日：2016-09-22

    申请号：US15072141

    申请日：2016-03-16

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Mikhaïl Baklanov ,  Liping Zhang ,  Jean-Francois de Marneffe

    IPC: H01J37/32

    CPC classification number: H01J37/32009 ,  H01J2237/334 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76826

    Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to plasma etching of dielectric materials having pores. In one aspect, a method for etching a porous material in an environment includes contacting the porous material with an organic gas at a pressure and a temperature. The organic gas is such that at the pressure and the temperature, the organic gas remains in a gas state when outside of the porous material, while the organic gas condenses into an organic liquid upon contacting the porous material. Upon contacting the porous material, the organic gas thereby fills the pores of the porous material with the organic liquid. Subsequent to contacting the porous material, the method additionally includes plasma etch-treating of the porous material having filled pores, thereby evaporating a fraction of the organic liquid filling the pores of the porous material.

    Abstract translation: 所公开的技术通常涉及半导体制造，更具体地涉及具有孔的电介质材料的等离子体蚀刻。 一方面，在环境中蚀刻多孔材料的方法包括在压力和温度下使多孔材料与有机气体接触。 有机气体使得在压力和温度下，有机气体在多孔材料外部保持为气态，而有机气体在与多孔材料接触时冷凝成有机液体。 当接触多孔材料时，有机气体由此用有机液体填充多孔材料的孔隙。 在多孔材料接触之后，该方法另外包括等离子体蚀刻处理具有填充孔的多孔材料，由此蒸发填充多孔材料的孔的有机液体的一部分。

    Plasma method for reducing post-lithography line width roughness
    3.
    发明授权
    Plasma method for reducing post-lithography line width roughness 有权
    等离子体方法，用于减小光刻后线宽度粗糙度

    公开(公告)号：US09520298B2

    公开(公告)日：2016-12-13

    申请号：US14616672

    申请日：2015-02-07

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Peter De Schepper ,  Jean-Francois de Marneffe ,  Efrain Altamirano Sanchez

    IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/027

    CPC classification number: H01L21/3086 ,  H01L21/0273

    Abstract: The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and −110° C. The plasma treatment may be a H2 plasma treatment performed in an inductively coupled plasma reactor. The treatment time may be at least 30s.

    Abstract translation: 本公开涉及一种用于处理衬底上的光致抗蚀剂结构的方法，所述方法包括在衬底上制造一个或多个抗蚀剂结构，将衬底引入等离子体反应器中，并使衬底在较低温度下进行等离子体处理 例如在零到-110℃之间。等离子体处理可以是在电感耦合等离子体反应器中进行的H 2等离子体处理。 治疗时间可能至少为30s。

    METHOD AND APPARATUS FOR REAL-TIME MONITORING OF PLASMA ETCH UNIFORMITY
    4.
    发明申请
    METHOD AND APPARATUS FOR REAL-TIME MONITORING OF PLASMA ETCH UNIFORMITY 有权
    实时监测等离子体均匀性的方法与装置

    公开(公告)号：US20160181165A1

    公开(公告)日：2016-06-23

    申请号：US14958771

    申请日：2015-12-03

    Applicant: IMEC VZW

    Inventor： Vladimir Samara ,  Jean-Francois de Marneffe

    IPC: H01L21/66 ,  H01L21/3065

    CPC classification number: H01L22/12 ,  G01B11/30 ,  H01J37/32935 ,  H01J37/32963 ,  H01J37/32972 ,  H01L21/3065

    Abstract: A method is provided for in-situ monitoring of etch uniformity during plasma etching, on the basis of the detection of interferometry patterns. The method is applicable to a reactor wherein a plasma is created in the area between the surface to be etched and a counter-surface arranged essentially parallel to the surface to be etched. The occurrence of interference patterns is detected at a location that is placed laterally with respect to the area between the surface to be etched and the counter-surface. The presence of an interference pattern at a particular wavelength is observed through the detection of oscillations of the light intensity measured by an optical detector, preferably by the standard Optical Emission Spectrometry tool of the reactor. When these oscillations are no longer detectable, non-uniformity exceeds a pre-defined limit. The counter surface is arranged such that the oscillations are detected.

    Abstract translation: 提供了一种用于在等离子体蚀刻期间基于干涉测量图案的检测来原位监测蚀刻均匀性的方法。 该方法适用于在被蚀刻表面和基本上平行于被蚀刻表面布置的对置面之间产生等离子体的反应器。 在相对于要被蚀刻的表面和对置表面之间的区域横向放置的位置处检测到干涉图案的发生。 通过检测由光学检测器测量的光强度的振荡，优选通过反应器的标准光学发射光谱测定工具来观察特定波长处的干涉图案的存在。 当这些振荡不再可检测时，不均匀性超过预定义的极限。 相对表面被布置成使得检测到振荡。

    Plasma Method for Reducing Post-Lithography Line Width Roughness
    5.
    发明申请
    Plasma Method for Reducing Post-Lithography Line Width Roughness 有权
    等离子体方法减少后平版印刷线宽度粗糙度

    公开(公告)号：US20150228497A1

    公开(公告)日：2015-08-13

    申请号：US14616672

    申请日：2015-02-07

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Peter De Schepper ,  Jean-Francois de Marneffe ,  Efrain Altamirano Sanchez

    IPC: H01L21/308 ,  H01L21/3065

    CPC classification number: H01L21/3086 ,  H01L21/0273

    Abstract: The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and −110° C. The plasma treatment may be a H2 plasma treatment performed in an inductively coupled plasma reactor. The treatment time may be at least 30 s.

    Abstract translation: 本公开涉及一种用于处理衬底上的光致抗蚀剂结构的方法，所述方法包括在衬底上制造一个或多个抗蚀剂结构，将衬底引入等离子体反应器中，并使衬底在较低温度下进行等离子体处理 例如在零到-110℃之间。等离子体处理可以是在电感耦合等离子体反应器中进行的H 2等离子体处理。 治疗时间可以至少30秒。

    Plasma etching of porous substrates
    6.
    发明授权
    Plasma etching of porous substrates 有权
    多孔基材的等离子体蚀刻

    公开(公告)号：US09595422B2

    公开(公告)日：2017-03-14

    申请号：US15072141

    申请日：2016-03-16

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Mikhaïl Baklanov ,  Liping Zhang ,  Jean-Francois de Marneffe

    IPC: B31D3/00 ,  H01J37/32 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

    CPC classification number: H01J37/32009 ,  H01J2237/334 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76826

    Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to plasma etching of dielectric materials having pores. In one aspect, a method for etching a porous material in an environment includes contacting the porous material with an organic gas at a pressure and a temperature. The organic gas is such that at the pressure and the temperature, the organic gas remains in a gas state when outside of the porous material, while the organic gas condenses into an organic liquid upon contacting the porous material. Upon contacting the porous material, the organic gas thereby fills the pores of the porous material with the organic liquid. Subsequent to contacting the porous material, the method additionally includes plasma etch-treating of the porous material having filled pores, thereby evaporating a fraction of the organic liquid filling the pores of the porous material.

    Abstract translation: 所公开的技术通常涉及半导体制造，更具体地涉及具有孔的电介质材料的等离子体蚀刻。 一方面，在环境中蚀刻多孔材料的方法包括在压力和温度下使多孔材料与有机气体接触。 有机气体使得在压力和温度下，有机气体在多孔材料外部保持为气态，而有机气体在与多孔材料接触时冷凝成有机液体。 当接触多孔材料时，有机气体由此用有机液体填充多孔材料的孔隙。 在多孔材料接触之后，该方法另外包括等离子体蚀刻处理具有填充孔的多孔材料，由此蒸发填充多孔材料的孔的有机液体的一部分。

    Methods and Systems for Forming a Mask Layer
    8.
    发明申请
    Methods and Systems for Forming a Mask Layer 审中-公开

    公开(公告)号：US20190057859A1

    公开(公告)日：2019-02-21

    申请号：US16103370

    申请日：2018-08-14

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Jean-Francois de Marneffe

    IPC: H01L21/027 ,  H01L21/033

    Abstract: In one aspect, the present disclosure relates to a method. The method includes providing a substrate having a patterned layer thereon, the patterned layer including an opening that exposes the substrate. The method also includes selectively infiltrating the patterned layer with a metal or ceramic material, thereby reducing a dimension of the opening. The opening exposes the substrate after the dimension of the opening is reduced.

    Semiconductor device manufacturing method
    10.
    发明授权
    Semiconductor device manufacturing method 有权

    公开(公告)号：US10910259B2

    公开(公告)日：2021-02-02

    申请号：US16213119

    申请日：2018-12-07

    Applicant: TOKYO ELECTRON LIMITED ,  IMEC VZW

    Inventor： Koichi Yatsuda ,  Tatsuya Yamaguchi ,  Yannick Feurprier ,  Frederic Lazzarino ,  Jean-Francois de Marneffe ,  Khashayar Babaei Gavan

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105

    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

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