公开(公告)号：US10957793B2

公开(公告)日：2021-03-23

申请号：US16128386

申请日：2018-09-11

Applicant: IMEC vzw

Inventor： Vasile Paraschiv ,  Guglielma Vecchio ,  Anabela Veloso

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure. Thereafter, the exposed target layer is removed along the upper portion of the sidewall surface of the vertical nanostructure selective towards the protection layer. Thereafter, the remaining protection layer is removed.

公开(公告)号：US09502264B2

公开(公告)日：2016-11-22

申请号：US14827774

申请日：2015-08-17

Applicant: IMEC VZW

Inventor： Eddy Kunnen ,  Vasile Paraschiv

IPC: H01L21/302 ,  H01L21/311 ,  C01B35/06 ,  C09K13/00 ,  H01L21/768

CPC classification number: H01L21/31144 ,  C01B35/061 ,  C09K13/00 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.

Abstract translation: 公开了一种用于去除至少包含硅和至少氮的材料选择性的氧化物的方法，所述方法包括在反应器中提供具有包含区域的表面的结构，其中所述区域包括至少包含硅和至少氮 在所述结构上提供覆盖所述区域的至少一部分的氧化物层，以及通过蚀刻去除对所述材料选择性的所述氧化物层，从而暴露所述区域的所述至少覆盖部分的至少一部分，其中所述蚀刻完成 仅通过提供包含硼的蚀刻剂气体，由此将低于30V的电压偏压施加到该结构。

公开(公告)号：US10825682B2

公开(公告)日：2020-11-03

申请号：US15258838

申请日：2016-09-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Vasile Paraschiv ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  B82Y40/00 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/28

Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

公开(公告)号：US20190097047A1

公开(公告)日：2019-03-28

申请号：US16128386

申请日：2018-09-11

Applicant: IMEC vzw

Inventor： Vasile Paraschiv ,  Guglielma Vecchio ,  Anabela Veloso

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure. Thereafter, the exposed target layer is removed along the upper portion of the sidewall surface of the vertical nanostructure selective towards the protection layer. Thereafter, the remaining protection layer is removed.

公开(公告)号：US20170103889A1

公开(公告)日：2017-04-13

申请号：US15258838

申请日：2016-09-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Vasile Paraschiv ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308

Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

公开(公告)号：US20160049310A1

公开(公告)日：2016-02-18

申请号：US14827774

申请日：2015-08-17

Applicant: IMEC VZW

Inventor： Eddy Kunnen ,  Vasile Paraschiv

IPC: H01L21/311 ,  C09K13/00 ,  C01B35/06

CPC classification number: H01L21/31144 ,  C01B35/061 ,  C09K13/00 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.

Abstract translation: 公开了一种用于去除至少包含硅和至少氮的材料选择性的氧化物的方法，所述方法包括在反应器中提供具有包含区域的表面的结构，其中所述区域包括至少包含硅和至少氮 在所述结构上提供覆盖所述区域的至少一部分的氧化物层，以及通过蚀刻去除对所述材料选择性的所述氧化物层，从而暴露所述区域的所述至少覆盖部分的至少一部分，其中所述蚀刻完成 仅通过提供包含硼的蚀刻剂气体，由此将低于30V的电压偏压施加到该结构。

公开(公告)号：US20150064889A1

公开(公告)日：2015-03-05

申请号：US14470462

申请日：2014-08-27

Applicant: IMEC VZW

Inventor： Vasile Paraschiv ,  Gustaf Winroth ,  Efrain Altamirano Sanchez ,  Sabrina Locorotondo ,  Raja Athimulam

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/266

CPC classification number: H01L21/0276 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821

Abstract: The present disclosure is related to a method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas. The method includes depositing an etch stop layer on the fins, depositing a BARC layer on the etch stop layer, depositing a resist layer on the BARC layer, removing a portion of the resist layer by lithography steps to thereby expose an area of the BARC layer, removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask, implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask, and removing the remainder of the resist and BARC layers.

Abstract translation: 本公开涉及用于在包括由场介电区域分离的多个半导体鳍片的结构中注入掺杂剂元素的方法。 该方法包括在鳍片上沉积蚀刻停止层，在蚀刻停止层上沉积BARC层，在BARC层上沉积抗蚀剂层，通过光刻步骤去除抗蚀剂层的一部分，从而暴露BARC层的一个区域 通过使用剩余的抗蚀剂层作为掩模的干蚀刻工艺去除曝光区域中的BARC层，使用BARC和抗蚀剂层作为掩模将掺杂剂元素注入到存在于该区域中的散热片中，并且除去其余的 抗蚀剂和BARC层。