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公开(公告)号：US20250105486A1
公开(公告)日：2025-03-27
申请号：US18474239
申请日：2023-09-26
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Shu-Jung Yang , Feng-Hsiang Lo , Yu-Lin Chao
Abstract: An antenna-in-package with a heat dissipation structure includes a circuit board, an antenna substrate, a chip, a plurality of heat dissipation fins, a chassis, and dielectric fluid. The circuit board has a first surface and a second surface opposite to the first surface. The antenna substrate is disposed above the first surface of the circuit board. The chip is disposed between the antenna substrate and the first surface of the circuit board and is electrically connected to the antenna substrate. The plurality of heat dissipation fins protrude from the second surface of the circuit board. The chassis encapsulates the circuit board, the antenna substrate, the chip, and the plurality of heat dissipation fins. The dielectric fluid circulates and flows in the chassis through a cooling circulation device and is in direct contact with the plurality of heat dissipation fins.
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2.发明授权公开(公告)号：US09448121B2
公开(公告)日：2016-09-20
申请号：US13854139
申请日：2013-04-01
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Ming-Ji Dai , Sheng-Tsai Wu , Huey-Lin Hsieh , Jing-Yi Huang
Abstract: A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.
Abstract translation: 提供了一种用于测量热电模块的测量方法，测量装置和计算机程序产品。 向热电模块提供温度。 向热电模块施加电流以将热电模块的两侧转变成热侧和冷侧。 热侧的温度高于冷侧的温度。 在不同的时间点测量热电模块的端电压，热侧的热侧温度和冷侧的冷侧温度。 根据端子电压，热侧温度和冷侧温度，获得端子电压与热侧温度与相应的冷侧温度之间的差异的热电关系。 根据热电关系估计热电模块的至少一个第一参数。
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公开(公告)号：US11942396B2
公开(公告)日：2024-03-26
申请号：US17564219
申请日：2021-12-29
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Shu-Jung Yang , Yu-Min Lin , Chih-Yao Wang , Yu-Lin Chao
IPC: H01L23/427 , H01L23/00 , H01L23/48 , H01L23/498 , H01L25/065
CPC classification number: H01L23/427 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/16 , H01L25/0655 , H01L2224/16235
Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.
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公开(公告)号：US20230170279A1
公开(公告)日：2023-06-01
申请号：US17564219
申请日：2021-12-29
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Shu-Jung Yang , Yu-Min Lin , Chih-Yao Wang , Yu-Lin Chao
IPC: H01L23/427 , H01L25/065 , H01L23/00 , H01L23/498 , H01L23/48
CPC classification number: H01L23/427 , H01L25/0655 , H01L24/16 , H01L23/49816 , H01L23/49833 , H01L23/49822 , H01L23/49838 , H01L23/481 , H01L2224/16235
Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.
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公开(公告)号：US11602128B2
公开(公告)日：2023-03-14
申请号：US16885250
申请日：2020-05-27
Applicant: Industrial Technology Research Institute
Inventor： Shu-Jung Yang , Yu-Lin Chao , Chih-Chung Chiu , Heng-Chieh Chien
Abstract: An ear tag module includes a rod member, a spike, a circuit component, and a temperature sensor. The spike is disposed on one side of the rod member, and the circuit component is disposed on another side of the rod member. The temperature sensor is electrically connected to the circuit component. When the spike penetrates an ear, the ear is in contact with a sensing area of the rod member, and the temperature sensor is located in the rod member to detect a temperature of the ear and transmit at least one temperature sensing information to the circuit component.
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Patent Agency Ranking
公开(公告)号：US10540474B2
公开(公告)日：2020-01-21
申请号：US15922910
申请日：2018-03-15
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Sheng-Tsai Wu , Ming-Ji Dai , Chih-Ming Shen
IPC: G06F17/50
Abstract: A chip temperature computation method and a chip temperature computation device are provided. The chip temperature computation method includes: computing an upper layer thermal resistance and a lower layer thermal resistance of a chip, computing a total thermal resistance of the chip, and computing a temperature of the chip according to the total thermal resistance.
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公开(公告)号：US20180128468A1
公开(公告)日：2018-05-10
申请号：US15479733
申请日：2017-04-05
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Yu-Lin Chao , Wen-Fu Hsu , Chih-Ming Shen , Chia-Wei Jui , Yao-Shun Chen
CPC classification number: F21V21/35 , F21V19/0045 , F21V21/14 , F21V23/06 , F21Y2115/15 , H01R25/142 , Y02B20/36
Abstract: A rail-type organic light emitting diode lamp assembly is provided. The lamp assembly includes a lamp module, an annular member, a connector, a conductive member, and a rail module. The annular member includes a protrusion portion having a pair of indentations. The connector is connected to the annular member, and includes a through hole, a first end provided with a pair of ears and a second end provided with a pair of hooks. The conductive member is provided in the through hole and has a first end in contact with the annular conductive coil. The rail module is connected with the connector and includes a conductor in contact with a second end of the conductive member. The connector can be slidably hooked to the rail module through the hooks, and after the ears are inserted into the indentations, the annular member can be rotatable with respect to the connector.
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公开(公告)号：US09418921B2
公开(公告)日：2016-08-16
申请号：US14965909
申请日：2015-12-11
Applicant: Industrial Technology Research Institute
Inventor： Shu-Jung Yang , Yu-Lin Chao , Heng-Chieh Chien , Chun-Kai Liu
IPC: H01L23/34 , H01L23/495 , H01L25/18 , H01L25/07 , H01L23/498
CPC classification number: H01L23/49575 , H01L23/13 , H01L23/3735 , H01L23/492 , H01L23/49562 , H01L23/49568 , H01L23/49811 , H01L23/49861 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/072 , H01L25/18 , H01L2224/04105 , H01L2224/06181 , H01L2224/2518 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2224/83447 , H01L2924/00014 , H01L2224/291 , H01L2924/014
Abstract: A power module includes a first substrate, at least two power elements, at least one first conductive structure and at least one leadframe. The first substrate includes a dielectric frame, two first fan-out circuit structure layers and two dielectric plates. The two first fan-out circuit structure layers are respectively disposed on two opposite surfaces of the dielectric frame, the two dielectric plates are respectively disposed on the two first fan-out circuit structure layers, each of the dielectric plates has at least one opening, and the opening and the corresponding first fan-out circuit structure layer form a concavity. The two power elements are respectively embedded in the two concavities. The two power elements are electrically connected to each other through the first conductive structure. The leadframe disposed at the first substrate is electrically connected to the two power elements, and is partially extended outside the first substrate.
Abstract translation: 功率模块包括第一衬底，至少两个功率元件，至少一个第一导电结构和至少一个引线框架。 第一基板包括电介质框架，两个第一扇出电路结构层和两个电介质板。 两个第一扇出电路结构层分别设置在电介质框架的两个相对表面上，两个电介质板分别设置在两个第一扇出电路结构层上，每个电介质板具有至少一个开口， 并且开口和相应的第一扇出电路结构层形成凹陷。 两个功率元件分别嵌入两个凹面。 两个功率元件通过第一导电结构彼此电连接。 设置在第一基板处的引线框架电连接到两个功率元件，并且部分地延伸到第一基板的外部。
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公开(公告)号：US20160172285A1
公开(公告)日：2016-06-16
申请号：US14965909
申请日：2015-12-11
Applicant: Industrial Technology Research Institute
Inventor： Shu-Jung Yang , Yu-Lin Chao , Heng-Chieh Chien , Chun-Kai Liu
IPC: H01L23/495 , H01L25/07 , H01L23/498 , H01L25/18
CPC classification number: H01L23/49575 , H01L23/13 , H01L23/3735 , H01L23/492 , H01L23/49562 , H01L23/49568 , H01L23/49811 , H01L23/49861 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/072 , H01L25/18 , H01L2224/04105 , H01L2224/06181 , H01L2224/2518 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2224/83447 , H01L2924/00014 , H01L2224/291 , H01L2924/014
Abstract: A power module includes a first substrate, at least two power elements, at least one first conductive structure and at least one leadframe. The first substrate includes a dielectric frame, two first fan-out circuit structure layers and two dielectric plates. The two first fan-out circuit structure layers are respectively disposed on two opposite surfaces of the dielectric frame, the two dielectric plates are respectively disposed on the two first fan-out circuit structure layers, each of the dielectric plates has at least one opening, and the opening and the corresponding first fan-out circuit structure layer form a concavity. The two power elements are respectively embedded in the two concavities. The two power elements are electrically connected to each other through the first conductive structure. The leadframe disposed at the first substrate is electrically connected to the two power elements, and is partially extended outside the first substrate.
Abstract translation: 功率模块包括第一衬底，至少两个功率元件，至少一个第一导电结构和至少一个引线框架。 第一基板包括电介质框架，两个第一扇出电路结构层和两个电介质板。 两个第一扇出电路结构层分别设置在电介质框架的两个相对表面上，两个电介质板分别设置在两个第一扇出电路结构层上，每个电介质板具有至少一个开口， 并且开口和相应的第一扇出电路结构层形成凹陷。 两个功率元件分别嵌入两个凹面。 两个功率元件通过第一导电结构彼此电连接。 设置在第一基板处的引线框架电连接到两个功率元件，并且部分地延伸到第一基板的外部。
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公开(公告)号：US20190188357A1
公开(公告)日：2019-06-20
申请号：US15922910
申请日：2018-03-15
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Sheng-Tsai Wu , Ming-Ji Dai , Chih-Ming Shen
IPC: G06F17/50
Abstract: A chip temperature computation method and a chip temperature computation device are provided. The chip temperature computation method includes: computing an upper layer thermal resistance and a lower layer thermal resistance of a chip, computing a total thermal resistance of the chip, and computing a temperature of the chip according to the total thermal resistance.
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