公开(公告)号：US09419619B2

公开(公告)日：2016-08-16

申请号：US14868451

申请日：2015-09-29

Applicant: Infineon Technologies AG

Inventor： Georg Tempel ,  Rolf-Peter Vollertsen

IPC: G11C11/00 ,  H03K19/177 ,  H03K19/003 ,  G11C13/00

CPC classification number: H03K19/17708 ,  G11C13/0007 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/20 ,  G11C16/26 ,  G11C2213/32 ,  H03K19/00315 ,  H03K19/17764

Abstract: A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction.

Abstract translation: 芯片包括具有多个晶体管并被配置为执行逻辑数据处理功能的逻辑电路，在执行数据处理功能时晶体管沿第一方向工作;以及读出电路，被配置为控制 逻辑电路以这样的方式使得晶体管在与第一方向相反的第二方向上操作，并且被配置为基于在第二方向上操作晶体管时来自逻辑电路的输出来确定逻辑电路的标识。

公开(公告)号：US09460810B2

公开(公告)日：2016-10-04

申请号：US14989822

申请日：2016-01-07

Applicant: Infineon Technologies AG

Inventor： Georg Tempel

IPC: G11C29/00 ,  G11C29/04 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  H01L21/66

CPC classification number: G11C29/04 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0403 ,  H01L22/14

Abstract: A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.

公开(公告)号：US08629034B2

公开(公告)日：2014-01-14

申请号：US13743369

申请日：2013-01-17

Applicant: Infineon Technologies AG

Inventor： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

IPC: H01L21/20

CPC classification number: H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

Abstract translation: 提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。

公开(公告)号：US09263154B2

公开(公告)日：2016-02-16

申请号：US14335972

申请日：2014-07-21

Applicant: Infineon Technologies AG

Inventor： Georg Tempel

IPC: G11C29/00 ,  G11C29/04

CPC classification number: G11C29/04 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0403 ,  H01L22/14

Abstract: A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.

Abstract translation: 描述了一种用于评估芯片制造过程的方法，其包括针对芯片制造过程中制造的多个芯片中的每一个测量芯片的位故障率，从测量的比特故障率确定比特故障率的分布; 从给定的芯片故障率限制确定最大允许位故障率，确定表示芯片制造过程中制造的芯片低于最大允许位故障率的概率的值，并基于该值确定芯片制造 过程适用于芯片故障率限制。

公开(公告)号：US20150129950A1

公开(公告)日：2015-05-14

申请号：US14576463

申请日：2014-12-19

Applicant: Infineon Technologies AG

Inventor： Georg Tempel ,  Ernst-Otto Andersen ,  Achim Gratz

IPC: H01L27/115 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/768 ,  H01L23/535 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

公开(公告)号：US20160019979A1

公开(公告)日：2016-01-21

申请号：US14335972

申请日：2014-07-21

Applicant: Infineon Technologies AG

Inventor： Georg Tempel

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0403 ,  H01L22/14

Abstract: A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.

公开(公告)号：US09299712B2

公开(公告)日：2016-03-29

申请号：US14576463

申请日：2014-12-19

Applicant: Infineon Technologies AG

Inventor： Georg Tempel ,  Ernst-Otto Andersen ,  Achim Gratz

IPC: H01L29/76 ,  H01L27/115 ,  H01L21/28 ,  H01L49/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/768 ,  H01L23/535 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract translation: 公开了制造半导体器件的半导体器件和方法。 提供半导体本体，浮置栅极多晶硅和源极/漏极区域。 提供了具有控制栅极节点的金属互连区域，其电容耦合到浮动栅极聚合物。

公开(公告)号：US20130130470A1

公开(公告)日：2013-05-23

申请号：US13743369

申请日：2013-01-17

Applicant: Infineon Technologies AG

Inventor： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

Abstract translation: 提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。