公开(公告)号：US20240420968A1

公开(公告)日：2024-12-19

申请号：US18738124

申请日：2024-06-10

Applicant: Infineon Technologies AG

Inventor： Alexander Schmer ,  Anita Herzer ,  Hans Hartung ,  Martin Goldammer

IPC: H01L21/56 ,  H01L23/02 ,  H01L23/31 ,  H01L25/07

Abstract: A method for forming a power semiconductor module arrangement includes: arranging a housing on a substrate, the housing having sidewalls and being arranged to directly adjoin the substrate such that the substrate forms a ground surface of the housing; filling a liquid, viscous or semi-liquid UV-curable potting material into the housing so as to cover the substrate with the potting material; irradiating a first portion of the potting material in areas of the potting material near an interface between the substrate and the sidewalls so as to seal any gaps between the substrate and the sidewalls; and irradiating a second portion of the potting material farther away from the interface between the substrate and the sidewalls than the first portion of the potting material to form an encapsulant. Irradiation of the first and second portions of the potting material takes place at different times and/or via different radiation sources.

公开(公告)号：US20230360982A1

公开(公告)日：2023-11-09

申请号：US18141634

申请日：2023-05-01

Applicant: Infineon Technologies AG

Inventor： Martin Goldammer ,  Ulrich Nolten ,  Christian Steininger ,  Carsten Ehlers

IPC: H01L23/10 ,  H01L23/04 ,  H01L23/12

CPC classification number: H01L23/10 ,  H01L23/04 ,  H01L23/12 ,  H01L23/06

Abstract: A method includes: pouring a liquid, semi-liquid or viscous material into a cavity formed by sidewalls of a housing, to cover a substrate that is arranged in the cavity formed by the sidewalls; arranging a lid on the sidewalls, to cover the cavity formed by the sidewalls, the lid including at least one functional element that extends from the lid into the liquid, semi-liquid or viscous material in a direction towards the substrate once the lid is in a final mounting position; and curing the liquid, semi-liquid or viscous material, to form a casting compound.

公开(公告)号：US20250062175A1

公开(公告)日：2025-02-20

申请号：US18802475

申请日：2024-08-13

Applicant: Infineon Technologies AG

Inventor： Charles Rimbert-Riviere ,  Georg Troska ,  Lydia Lottspeich ,  Martin Goldammer ,  Ulrich Wilke ,  Benedikt Domes ,  Lars Böwer

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L25/07

Abstract: A method for producing a substrate for a semiconductor module includes: forming a first electrically conductive layer on a first side of a dielectric insulation layer; structuring the first electrically conductive layer by creating one or more incisions through the first electrically conductive layer that extend from an upper surface of the first electrically conductive layer down to the dielectric insulation layer, thereby completely separating different sections of the first electrically conductive layer; and forming a passivation layer covering the entire upper surface of the structured first electrically conductive layer.

公开(公告)号：US12205826B2

公开(公告)日：2025-01-21

申请号：US17202849

申请日：2021-03-16

Applicant: Infineon Technologies AG

Inventor： Charles Rimbert-Riviere ,  Martin Goldammer ,  Lydia Lottspeich ,  Ulrich Wilke

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A method for forming a semiconductor substrate arrangement includes: forming a mask on a semiconductor substrate, the semiconductor substrate including and a metallization layer arranged on an insulation layer, the metallization layer arranged between the mask and insulation layer; forming a layer of electrically conductive coating on the metallization layer, the electrically conductive coating formed in at least one opening of the mask on regions of the metallization layer that are not covered by the mask; and after forming the electrically conductive coating, removing the mask. Forming the mask includes either applying an even layer of material on the metallization layer, or applying the material of the mask on the metallization layer such that the thickness of the mask in a region adjacent to edges of the mask is greater than the thickness of the regions of the mask further away from the edges.

公开(公告)号：US20240071853A1

公开(公告)日：2024-02-29

申请号：US18140132

申请日：2023-04-27

Applicant: Infineon Technologies AG

Inventor： Hans Hartung ,  Martin Goldammer ,  Carsten Ehlers ,  Katja Engelkemeier ,  Guido Bönig

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/053 ,  H01L25/11

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/053 ,  H01L24/48 ,  H01L25/115 ,  H01L2224/48091 ,  H01L2224/48225

Abstract: A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.

公开(公告)号：US20230343681A1

公开(公告)日：2023-10-26

申请号：US18138245

申请日：2023-04-24

Applicant: Infineon Technologies AG

Inventor： Andre Arens ,  Martin Goldammer

IPC: H01L23/49 ,  H01L25/07 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49 ,  H01L25/072 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L21/565 ,  H01L2224/32225 ,  H01L2224/48155 ,  H01L2224/73265 ,  H01L2924/182

Abstract: A power semiconductor module arrangement includes a housing that includes sidewalls, a lid, protrusions, a substrate, a plurality of components arranged on the substrate, and an encapsulant partly filling the interior of the housing, thereby covering the substrate, wherein each of the protrusions extends from the lid of the housing, a lower end of the protrusions is arranged directly on one of the components, or within a defined radius around one of the components, and wherein the lower end of a protrusion is the end facing away from the lid and towards the substrate, and the encapsulant has a generally flat surface and forms one or more elevations, wherein each of the elevations encloses an upper end of a different one of the components, and encloses the lower end of a respective one of the protrusions.

公开(公告)号：US20210305062A1

公开(公告)日：2021-09-30

申请号：US17202849

申请日：2021-03-16

Applicant: Infineon Technologies AG

Inventor： Charles Rimbert-Riviere ,  Martin Goldammer ,  Lydia Lottspeich ,  Ulrich Wilke

IPC: H01L21/48 ,  H01L23/498

Abstract: A method for forming a semiconductor substrate arrangement includes: forming a mask on a semiconductor substrate, the semiconductor substrate including and a metallization layer arranged on an insulation layer, the metallization layer arranged between the mask and insulation layer; forming a layer of electrically conductive coating on the metallization layer, the electrically conductive coating formed in at least one opening of the mask on regions of the metallization layer that are not covered by the mask; and after forming the electrically conductive coating, removing the mask. Forming the mask includes either applying an even layer of material on the metallization layer, or applying the material of the mask on the metallization layer such that the thickness of the mask in a region adjacent to edges of the mask is greater than the thickness of the regions of the mask further away from the edges.