公开(公告)号：US10475520B2

公开(公告)日：2019-11-12

申请号：US15821871

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C7/22 ,  G11C29/02 ,  G11C7/06 ,  G11C29/12 ,  G11C29/00 ,  G11C29/44

Abstract: A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

公开(公告)号：US10937469B2

公开(公告)日：2021-03-02

申请号：US16666425

申请日：2019-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C7/10 ,  G06F11/10 ,  G06F11/25 ,  G06F12/02 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/34 ,  H03M13/13 ,  G11C29/26

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

公开(公告)号：US20180158534A1

公开(公告)日：2018-06-07

申请号：US15831439

申请日：2017-12-05

Applicant: Infineon Technologies AG

Inventor： Jan OTTERSTEDT ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C29/34 ,  G11C16/10 ,  G06F11/25 ,  G06F12/02 ,  G11C16/26 ,  G11C16/08 ,  G06F11/10 ,  H03M13/13

CPC classification number: G11C29/34 ,  G06F11/1048 ,  G06F11/25 ,  G06F12/0246 ,  G11C7/1006 ,  G11C16/08 ,  G11C16/105 ,  G11C16/26 ,  G11C2029/2602 ,  H03M13/13

Abstract: In various embodiments, a memory circuit is provided. The memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, wherein each word portion is configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion comprising a plurality of overlay memory cells, wherein each of the plurality of overlay portions comprises an overlay word, wherein the memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, thereby providing, as an output of the read operation, a result of a logic operation performed on the data word and the overlay word.

公开(公告)号：US20180151244A1

公开(公告)日：2018-05-31

申请号：US15821871

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C29/02 ,  G11C7/06

CPC classification number: G11C29/025 ,  G11C7/06 ,  G11C29/12005 ,  G11C29/702 ,  G11C29/82 ,  G11C2029/1202 ,  G11C2029/4402

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a plurality of word lines, each word line coupled with one or more memory cells, a plurality of non-volatile marking memory cells, wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells, and a plurality of marking bit lines, each associated with marking memory cells, a plurality of marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.